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em78p259n/260n 8-bit microprocessor with otp rom product specification d oc . v ersion 1.0 elan microelectronics corp. june 2005
t r adem ark acknowledgm ents : ibm is a registered tradem ark and ps/2 is a tradem ark of ibm. w i ndows is a tradem ark of microsoft corporation. l a n a n d e l a n l o g o are tradem a r k s o f e l a n m i c r o e l e c t r o n i c s c o r p o r a t e i o n . l a n m i c r o e l e c t r o n i c s c o r p o r a t i o n e d r i n t e d i n t a iwan i cs assum e s o n t ai ned i n p ecial i n ci de nt al , or c ons eq ue nt i a l dam a ges ari s i n g f r o m t h e u s e of s u ch i n f o r m at i o n e o r n o n d i scl o sure agreem ent , and ces, or sy st em s. use of n y means w i thout the expressed w r itten permission of elan microelectronics. el an microelectronics c o rpora t ion d 1 http : //w w w .em c .com .tw copy right ? 2 0 0 5 b y e a l l r i g h t s r e s e r v p the cont ent s of t h i s speci fi cat i on are subject t o change wi t hout furt her not i ce. elan m i croel ect r o n no responsibility concerning the accuracy , adequacy , or com p leteness of this specification. elan m i croel ect roni cs m a kes no com m i t m ent t o updat e , or t o keep current t h e i n form at i on and m a t e ri al c this specification. such inform a tion and m a terial m a y change to conform to each confirm e d order . in no event shal l elan m i croel ect roni cs be m a de responsi b l e for any cl ai m s at t r i but ed t o errors, om i ssi ons, or ot he r i n acc urac i e s i n t h e i n f o r m at i on or m a t e ri al cont ai ne d i n t h i s s p eci fi ca t i on. el a n m i croel ect r oni cs shal l n o t be lia ble for direct, indirect, s or m a terial. the soft ware (i f any ) descri bed i n t h i s speci fi cat i on i s furni s hed under a l i c e n s m a y be used or copied only in accordance with the term s of such agreem ent. elan m i croel ect roni cs product s are not i n t e nded for use i n l i f e support appl i a n c e s , d e v i elan m i croel ect roni cs product i n such appl i cat i ons i s not support e d and i s prohi bi t e d. n o p a r t o f th is speci fica ti on ma y be reprodu ced o r tra n smi t ted i n any fo rm o r by a he a dqua rte r s : n o . 1 2 , i n n o v a t i o n r o a hsinchu science park hsinchu, t a iwan 308 tel : +886 3 563-9977 fa x : +886 3 563-9966 hong kong: elan (hk) micro e l e c t r o n i cs t r e i n g elanhk@emc.com.hk corpora t ion, lt d. r m . 1 0 0 5 b , 1 0 / f e m p i r e c e n 68 mody road, t s i m s h a t s u k o w l o o n , h o n g k o tel : +852 2723-3376 fa x : +852 2 7 2 3 - 7 7 8 0 usa : ela n i n f o r m a tion t e c hnology u i t e 2 5 0 g a , c a 95070 fa x : +1 408 366-8220 group 1821 saratoga a v e . , s s a r a t o usa tel : +1 408 366-8223 europe : elan m i c r o e lectro n i cs co rp . r l a n d http : //www. elan-europe. c om (europe ) siewerdtstrasse 105 8 0 5 0 z u r i c h , s w i t z e tel : +41 43 299-4060 fa x : +41 43 299-4079 sh en zh en : elan micro e l e c t r o n i cs k i n a fa x : +86 755 2601-0500 i b o r o a sh en zh en , l t d . ssmec bldg., 3f , gaoxin s. a v e. shenzhen hi-t e c h i n d u s t r i a l p a r s h e n z h e n , g u a n d o n g , c h tel : +86 755 2601-0565 sha ngha i: elan micro e lectro n i cs sha ngha i corpora t ion, lt d. 23/bldg. #1 1 5 l a n e 5 7 2 , b d p a r k fa x : +86 021 5080-4600 zhangjiang hi-t e c h shanghai, china tel : +86 021 5080-3866
conte n ts product specification (v1.0) 06.16.2005 ? iii contents 1 general description .................................................................................................. 1 2 features ..................................................................................................................... 1 3 pin configuration (package) .................................................................................... 2 3.1 em78p259np/m pin assignment....................................................................... 2 3.2 em78p260np/m/km pin assignment ................................................................ 3 4 functional block diagram........................................................................................ 3 5 pin description.......................................................................................................... 4 5.1 em78p259np/m pin description ....................................................................... 4 5.2 em78p260np/m/km pin description ................................................................. 5 6 function description ................................................................................................ 6 6.1 operational registers......................................................................................... 6 6.1.1 r0 (indirect a ddress regi ster) ............................................................................6 6.1.2 r1 (time cl ock /count er)....................................................................................6 6.1.3 r2 (program co unter) and stack........................................................................6 6.1.3.1 data memory configuration .................................................................8 6.1.4 r3 (statu s register) ............................................................................................9 6.1.5 r4 (ram sele ct register) ...................................................................................9 6.1.6 r5 ~ r6 (por t 5 ~ port 6) ..................................................................................10 6.1.7 r7 (p ort 7) .........................................................................................................10 6.1.8 r8 (aisr: adc input select regi ster) ..............................................................11 6.1.9 r9 (adcon: adc control register).................................................................12 6.1.10 ra (adoc: adc offset calibration r egister) ...................................................13 6.1.11 rb (addata: conv erted value of adc)...........................................................13 6.1.12 rc (addata1h: conv erted value of adc) ......................................................14 6.1.13 rd (addata1l: conv erted value of adc) ......................................................14 6.1.14 re (interrupt status 2 & wake-up contro l register) ........................................14 6.1.15 rf (interrupt st atus 2 regi ster) ........................................................................15 6.1.16 r10 ~ r3f .........................................................................................................15 6.2 special purpose registers ............................................................................... 16 6.2.1 a (accum ulator ).................................................................................................16 6.2.2 cont (contro l register)...................................................................................16 6.2.3 ioc50 ~ ioc70 (i/o po rt control re gister) ......................................................17 6.2.4 ioc80 (comparator and tcca control register).............................................17 6.2.5 ioc90 (tccb and tccc control regi ster ).....................................................18 6.2.6 ioca0 (ir and tccc sc ale control re gister) .................................................19 6.2.7 iocb0 (pull-down control register).................................................................21 6.2.8 iocc0 (open -drain control register) ..............................................................21
conte n ts iv ? product specification (v1.0) 06.16.2005 6.2.9 iocd0 (pull-high control regi ster)...................................................................22 6.2.10 ioce0 (wdt control & in terrupt mask registers 2) ........................................22 6.2.11 iocf0 (interrupt mask register).......................................................................23 6.2.12 ioc51 (tcca counter ) .....................................................................................24 6.2.13 ioc61 (tccb counter ) .....................................................................................24 6.2.14 ioc71 (tccbh/ msb coun ter) .........................................................................25 6.2.15 ioc81 (tccc counter).....................................................................................25 6.2.16 ioc91 (low-t ime regist er) ..............................................................................26 6.2.17 ioca1 (high ti me regist er) .............................................................................26 6.2.18 iocb1 high/low time scale control register) ................................................26 6.2.19 iocc1 (tcc pres caler count er) ......................................................................27 6.3 tcc/wdt and prescaler.................................................................................. 28 6.4 i/o ports ........................................................................................................... 29 6.4.1 usage of port 5 input chan ge wake-up/interr upt function..............................32 6.5 reset and wake-up ....................................................................................... 32 6.5.1 reset and wake -up operat ion .......................................................................32 6.5.1.1 wake-up and interrupt modes operat ion summa ry..........................35 6.5.1.2 register initial values afte r reset ......................................................37 6.5.1.3 controller rese t block di agram.........................................................42 6.5.2 the t and p status und er status regist er ....................................................42 6.6 interrupt ............................................................................................................ 42 6.7 analog-to-digital converter (adc) .................................................................. 45 6.7.1 adc control register (a isr/r8, adcon/r9 , adoc/ra) ...............................45 6.7.1.1 r8 (aisr: adc i nput select r egister) ...............................................45 6.7.1.2 r9 (adcon: adc control register)..................................................46 6.7.1.3 ra (adoc: adc offs et calibration register) ....................................47 6.7.2 adc data register (addata/ rb, addata1h/rc, addata1l/rd) ...............48 6.7.3 adc samp ling time ..........................................................................................48 6.7.4 ad conv ersion time .........................................................................................48 6.7.5 adc operation during sle ep mode ...................................................................48 6.7.6 programming proces s/considerations..............................................................49 6.7.6.1 programmi ng process........................................................................49 6.7.6.2 sample de mo programs ....................................................................50 6.8 infrared remote control application/pwm waveform generation................... 52 6.8.1 over view ...........................................................................................................52 6.8.2 function description..........................................................................................53 6.8.3 programming the related registers ................................................................55 6.9 timer/counter................................................................................................... 56 6.9.1 over view ...........................................................................................................56 6.9.2 function description..........................................................................................56 6.9.3 programming the re lated regi sters .................................................................58
conte n ts product specification (v1.0) 06.16.2005 ? v 6.10 comparator ...................................................................................................... 58 6.10.1 external re ference signal ................................................................................59 6.10.2 comparator outputs..........................................................................................60 6.10.3 using comparator as an operation am plifier....................................................60 6.10.4 comparator interr upt .........................................................................................60 6.10.5 wake-up from sleep mode .............................................................................60 6.11 oscillator .......................................................................................................... 61 6.11.1 oscilla tor mo des................................................................................................61 6.11.2 crystal oscillator/cer amic resonators (xtal) .................................................62 6.11.3 external rc oscillato r mode .............................................................................63 6.11.4 internal rc oscillator mode ..............................................................................64 6.12 power-on considerations ................................................................................. 65 6.12.1 programmable wdt time-out period ..............................................................65 6.12.2 external power- on reset ci rcuit .......................................................................65 6.12.3 residual vo ltage protec tion ..............................................................................66 6.13 code option ..................................................................................................... 67 6.13.1 code option r egister (w ord 0) .........................................................................67 6.13.2 code option r egister (w ord 1) .........................................................................68 6.13.3 customer id r egister (w ord 2) .........................................................................69 6.14 instruction set .................................................................................................. 69 7 absolute maximum ratings ................................................................................... 71 8 dc electrical characteristics ................................................................................. 72 8.1 ad converter characteristics........................................................................... 73 8.2 comparator (op) characteristics ..................................................................... 74 8.3 device characteristics...................................................................................... 74 9 ac electrical characteristic ................................................................................... 75 10 timing diagrams ..................................................................................................... 76 appendix a. package types summary ....................................................................................... 77 b packaging configurations...................................................................................... 77 b.1 18-lead plastic dual in line (pdip) - 300 mil ................................................... 77 b.2 18-lead plastic small outline (sop) - 300 mil ................................................ 78 b.3 20-lead plastic shrink small outline (ssop) - 209 mil ................................... 79 b.4 20-lead plastic dual-in-line (pdip) - 300 mil ................................................... 80 b.5 20-lead plastic small outline (sopp) - 300 mil .............................................. 81 c quality assurance and reliability ......................................................................... 82 c.1 address trap detect......................................................................................... 82
conte n ts vi ? product specification (v1.0) 06.16.2005 specification revision history doc. version revision description date 1.0 initial official version 2005/06/16
em78p259n/260n 8-bit microprocessor w i th otp rom product specification (v1.0) 06.16.2005 ? 1 (this specification is subject to change without further notice) 1 general description em78p259n and em78p260n are 8-bit micropr ocessors designed and developed with low-power and high-speed cmos technology. it is equipped with a 2k*13-bit electrical one time programmable read only memory (o tp-rom). with its otp-rom feature, it is able to offer a convenient way of devel oping and verifying your programs. moreover, it provides a protect bit to guard against code intrusion, as well as 3 code option words to accommodate your requirements. furt hermore you can take advantage of elan writer to easily write your developm ent code into the em78p259n and em78p260n. 2 features operating voltage range : 2.3v~5.5v base on 0 c ~ 70 c (commercial) 2.5v~5.5v base on ?40 c ~ 85 c (industrial) operating frequency range (base on 2 clocks): ? crystal mode: dc ~ 20mhz/2clks, 5v; dc ~ 8mhz/2clks, 3v ? rc mode: dc ~ 4mhz/2clks, 5v; dc ~ 4mhz/2clks, 3v low power consumption: ? less than 1.9 ma at 5v/4mhz ? typically 15 a, at 3v/32khz ? typically 1 a, during sleep mode built-in rc oscillator 4mhz, 8mhz,1mhz, 455khz (auto calibration) programmable wdt time (4.5ms : 18ms) independent programmable prescaler of wdt one configuration register to match y our requirements, and user?s id code for customer use is provided 80 8 on chip registers (sram, general purpose register) 2k 13 on-chip rom bi-directional i/o ports 8-level stacks for subroutine nesting 8-bit real time clock/counter (tcc) with se lective signal sources, trigger edges, and overflow interrupt 8-bit real time clock/counter (tcca, t ccc) and 16-bit real time clock/counter (tccb) with selective signal sources, trigger edges, and overflow interrupt one pair of comparators (can act as an op) 4-bit multi-channel analog-to-digital converter with 12-bit resolution
em78p259n/260n 8-bit microprocessor w i th otp rom 2 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) easily-implemented ir (infrared re mote control) application circuit power down (sleep) mode six interrupt sources : ? tcc, tcca, tccb, and tccc overflow interrupt ? input-port st atus change interr upt (wake-up from sleep mode) ? external interrupt ? comp arators st atus change interrupt ? ir/pwm interrupt ? adc completion interrupt programmable free running watchdog timer 8 programmable pull-high i/o pins 8 programmable open-drain i/o pins 8 programmable pull-down i/o pins. t w o or four clocks per inst ruct ion cy cle package types : ? 18-pin dip 300mil : em78p259np ? 18-pin sop 300mil : EM78P259NM ? 20-pin dip 300mil : em78p260np ? 20-pin sop 300mil : em78p260nm ? 20-pin ssop 209mil : em78p260nkm power-on volt age detector available (2.0v 0.1v) 3 pin configuration (package) 3.1 em78p259np/m pin assignment p 52/adc2 p 53/ad c3 p 5 4/tcc/v r ef /reset vs s p 60//i nt p 61/tcca p 62/tccb p6 3 / t c c c p 55/osci p7 0 / o s c o vd d p6 7 / i r o u t p 65/cin+ em78p25 9np em78p2 59nm 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 p 64/co 10 p 66/cin- p 5 0/adc0 p 51/ad c1 f i g. 3-1 pin assignment ? em78p259np/m
em78p259n/260n 8-bit microprocessor w i th otp rom produc t spe c i fic a t ion (v1.0) 06.16.2 005 ? 3 (this specification is subject to change without further notice) 3.2 em78p260np/m/km pin assignment 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 p52/ ad c2 p 53/ad c3 p54/ t cc/ vr e f /reset vs s p 60/ /int p6 1 / t c c a p62/t ccb p6 3 / t c c c p 55/ os ci p7 0 / o s c o vd d p67/ir out p 6 5/cin+ em 78p26 0n p6 4 / c o p 6 6/cin- p 5 0/ad c0 p 5 1/ad c1 p5 6 p 5 7 f i g. 3-2 pin assignment ? em78p260np/m/km 4 functional block diagram da t a & contr o l bus o s c illa t o r t i m i n g cont r o l wd t t i m e r p r esca le r ram r4 r 1 ( t cc) i n terru p t c o n t ro ll er ro m in st ru ct io n re g i s t e r r2 alu ac c r3 i n stru ctio n d eco d e r osc i os c o /r e s e t tc c /in t io c 5 r5 c o unt er stac k 6 i o c 6 / 7 r6/ 7 por t 5 i/o p 6 0 /in t p 61/ t c ca p 62/ t c cb p 63/ t c cc p 64/ c o p 65/ c i n+ p 66/ c i n- p 6 7 /ir o u t p 70/ o s c o a dc0 / p 5 0 a dc1 / p 5 1 a dc2 / p 5 2 a dc3 / p 5 3 vr ef /t cc /p 54 o s c i/p5 5 p56 p57 stack 7 stack 5 stack 4 stack 3 stack 2 stack 1 stack 0 b u i l t-i n osc i/ o po r t 6/7 f i g. 4-1 em78p259n/260n f unctional block diagram
em78p259n/260n 8-bit microprocessor w i th otp rom 4 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) 5 pin description 5.1 em78p259np/m pin description symbol pin no. type function vdd 14 ? power supply osci 16 i xtal type crystal input terminal or external clock input pin rc type : rc oscillator input pin osco 15 i/o xtal type : output terminal for crysta l oscillator or external clock input pin rc type : clock output with a duration one instruction cycle external clock signal input p70 15 i/o general-purpose i/o pin default value at power-on reset p60 ~ p67 6 ~ 13 i/o general-purpose i/o pin open drain default value at power-on reset p50 ~ p55 1 ~ 3 16 ~ 18 i/o general-purpose i/o pin pull-high/pull-down wake up from sleep mode when t he status of the pin changes default value at power-on reset cin?, cin+ co 12, 11 10 i o ??? the input pin of vi n? of a comparator ?+? the input pin of vin+ of a comparator pin co is the output of the comparator defined by ioc80 <4 : 3> ir out 13 o ir mode output pin. c apable of driving and sinking current = 20ma when the output voltage drops to 0.7vdd and rise to 0.3vdd at vdd = 5v. vref 3 i external reference voltage for adc defined by adcon (r9)<7> /int 6 i external interrupt pin triggered by falling or rising edge defined by cont <7> tcc, tcca, tccb, tccc 3, 7, 8, 9 i external counter input tcc defined by cont<5> tcca defined by ioc80 <1> tccb defined by ioc90 <5> tccc defined by ioc90 <1> adc0 ~ adc3 1, 2, 17, 18 i analog to digital converter defined by adcon (r9)<1:0> /reset 4 i if it remains at logic low, the device will be reset wake-up from sleep mode when pin status changes voltage on /reset/vpp must not exceed vdd during normal mode vss 5 ? ground
em78p259n/260n 8-bit microprocessor w i th otp rom product specification (v1.0) 06.16.2005 ? 5 (this specification is subject to change without further notice) 5.2 em78p260np/m/km pin description symbol pin no. type function vdd 15 ? power supply. osci 17 i xtal type crystal input terminal or external clock input pin rc type : rc oscillator input pin osco 16 i/o xtal type : output terminal for crysta l oscillator or external clock input pin rc type : clock output with a time period of one instruction cycle. external clock signal input p70 16 i/o general-purpose i/o pin default value at power-on reset p60 ~ p67 7 ~ 14 i/o general-purpose i/o pin open-drain default value at power-on reset p50 ~ p57 1 ~ 4 17 ~ 20 i/o general-purpose i/o pin pull-high/pull-down wake up from sleep mode when t he status of the pin changes default value at power-on reset cin?, cin+ co 13, 12 11 i o ??? the input pin of vi n? of a comparator ?+? the input pin of vin+ of a comparator pin co is the output of the comparator defined by ioc80 <4 : 3> ir out 14 o ir mode output pin. c apable of driving and sinking current = 20ma when the output voltage drops to 0.7vdd and rise to 0.3vdd at vdd = 5v. vref 4 i external reference voltage for adc defined by adcon (r9)<7> /int 7 i external interrupt pin triggered by falling or rising edge. defined by cont <7> tcc, tcca, tccb, tccc 4, 8, 9, 10 i external counter input tcc defined by cont<5> tcca defined by ioc80 <1> tccb defined by ioc90 <5> tccc defined by ioc90 <1> adc0 ~ adc3 2, 3, 18, 19 i analog to digital converter defined by adcon (r9)<1 : 0> /reset 5 i if it remains at logic low, the device will be reset wake-up from sleep mode when pin status changes voltage on /reset/vpp must not exceed vdd during normal mode vss 6 ? ground
em78p259n/260n 8-bit microprocessor w i th otp rom 6 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) 6 function description 6.1 operational registers 6.1.1 r0 (indirect address register) r0 is not a physically implemented register . it s major func tion is to perform as an indirect address pointer . any instruction us ing r0 as a pointer , actually accesses the dat a pointed by the ram select register (r4). 6.1.2 r1 (time clock /counter) increased by an external signal edge which is defined by the te bit (cont-4) through the tcc pin, or by t he instruction cycle clock. writable and readable as any other registers the tcc prescaler counter (iocc1) is assigned to tcc the contents of the iocc1 register is cleared whenever ? ? a value is written to tcc register . ? a value is written to tcc prescaler bit s (bit3, 2, 1, 0 of the cont register) ? during power on res e t, /reset , or wdt time out res e t. 6.1.3 r2 (program counter) and stack a7 ~ a0 on-c hi p p r og r a m me m o r y ) '') ) h a r d w a r e inte r r up t ve ct o r u s e r me mo r y spac e r e se t ve cto r a9 a8 a10 stack le ve l 1 st ac k l e v e l 3 st ac k l e v e l 2 st ac k l e v e l 4 st ac k l e v e l 5 cal l 0 0 pag e0 0 0 0 0 ~ 0 3 f f 0 1 pag e1 0 4 0 0 ~ 0 7 f f r3 re t re t l re t i st ac k l e v e l 6 st ac k l e v e l 7 st ac k l e v e l 8 &) _ ' &) f i g. 5-2 program counter organiz a tion r2 and hardware st acks are 12-bit wide. the structure is depicted in the t able under section 6.1.3.1, dat a mem o ry configuration (next p age). generates 2k 13 bit s on-chip rom addresses to the relative programming instruction codes. one program p age is 1024 words long. the content s of r2 are all set to "0"s when a reset condition occurs.
em78p259n/260n 8-bit microprocessor w i th otp rom product specification (v1.0) 06.16.2005 ? 7 (this specification is subject to change without further notice) "jmp" instruction allows direct loading of the lower 10 program counter bits. thus, "jmp" allows pc to jump to any location within a page. "call" instruction loads the lower 10 bits of the pc, and then pc+1 is pushed into the stack. thus, the subroutine entry address can be located anywhere within a page. "ret" ("retl k", "reti") instruction loads the program counter with the contents of the top of stack. "add r2, a" allows a relative address to be added to the current pc, and the ninth and above bits of the pc will increase progressively. "mov r2, a" allows loading of an address from the "a" register to the lower 8 bits of the pc, and the ninth and tenth bits (a8 ~ a9) of the pc will remain unchanged. any instruction (except ?add r2,a?) that is written to r2 (e.g., "mov r2, a", "bc r2, 6",?????) will cause the ninth bit and the tenth bit (a8 ~ a9) of the pc to remain unchanged. in the case of em78p259n/260n, the most significant bit (a10) will be loaded with the content of ps0 in the status register (r3) upon execution of a "jmp", "call", or any other instructions set which write to r2. all instructions are single instruction cy cle (fclk/2 or fclk/4) except for the instructions that are written to r2. no te that these instructions need one or two instructions cycle as determined by code option register cyes bit.
em78p259n/260n 8-bit microprocessor w i th otp rom 8 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) 6.1.3.1 dat a memory configuration ad d r e s s r page re g i s t e r s i o c x 0 pag e re gi s t ers 00 r0 ( i ndir e ct a ddr essing r egister ) re s e r v e 01 r1 ( t im e c l ock coun ter ) co nt ( c o n t ro l re gi s t er ) 02 r2 (pr o gr a m co un te r) res e rv e 03 r3 ( s tatus r egister ) re s e r v e 04 r4 (ram se le c t reg i s t e r ) re s e r v e 05 r5 (po r t 5 ) io c50 (i/o p o r t c ontr o l registe r ) 06 r6 (po r t 6 ) io c60 (i/o p o r t c ontr o l registe r ) 07 r7 (po r t 7 ) io c70 (i/o p o r t c ontr o l registe r ) 08 ( a dc i nput s e le ct reg i ste r 09 0a 0b io cb 0 (p u l l- dow n c ontr o l re gister) 0c 0d 0e 0f ioc f 0 ( i nte r r upt m a sk re gister 1 ) 10 m 1f gen e ra l register s 20 j 3f b a n k 0 b ank1 io cx 1 pag e re gi s t ers io c80 ( c om p a ra tor and t cca co n t ro l re gi s t er ) io c90 ( t cc b and t ccc co n t ro l re gi s t er ) io ca 0 ( i r an d t c cc s c ale co n t ro l re gi s t er ) io cc0 (o pen -dr a in c ontr o l re gister) io cd0 ( p ull- high c ontr o l reg i s t er) ioc e 0 ( w dt cont rol re gister and inte rr upt m a sk re gis t er 2 ) io c51 (t cca c ount er) io c61 ( t cc b ls b co unter ) io c7 1 (t c c b hs b c ount er) io c8 1 (t c cc c ount er) io c9 1 ( l ow - t im e re gi s t er ) io ca 1 ( h ig h- t i m e re gi s t er ) io cb 1 ( h igh- t i m e and low -t im e s c ale con t rol r egister ) reser v e reser v e reser v e reser v e reser v e reser v e reser v e reser v e (a dc con t rol r egister ) (adc off s et cal i br ation register ) (t he con v er ted v a lue ad 1 1 ~ ad4 o f adc ) (t h e conv er ted v a lue ad11~ad8 of adc) (t he con v er ted v a lue a d 7~a d 0 of a d c) (inte r r upt s t a t us 2 a n d w a ke- u p cont rol re gister (i nter rup t s t atus r egister 1) r9 ra rd re rf rb rc r8 io cc1 (t cc pr escaler control)
em78p259n/260n 8-bit microprocessor w i th otp rom product specification (v1.0) 06.16.2005 ? 9 (this specification is subject to change without further notice) 6.1.4 r3 (status register) 7 6 5 4 3 2 1 0 rst iocs ps0 t p z dc c bit 7 (rst): bit of reset type set to ?1? if wake-up from sleep on pin change, comparator status change, or ad conversion completed. set to ?0? if wake-up from other reset types bit 6 (iocs): select the segment of io control register 0 = segment 0 (ioc50 ~ iocf0) selected 1 = segment 1 (ioc51 ~ iocc1) selected bit 5 (ps0): page select bits. ps0 is used to select a program memory page. when executing a "jmp," "call," or ot her instructions which cause the program counter to change (e.g., mo v r2, a), ps0 is loaded into the 11th bit of the program counter w here it selects one of the available program memory pages. note that ret (retl, reti) instruction does not change the ps0 bit. that is, the return will always be back to the page from where the subroutine was called, regardless of the current ps0 bit setting. ps0 program memory page [address] 0 page 0 [000-3ff] 1 page 1 [400-7ff] bit 4 (t): time-out bit. set to ?1? by the "slep" and "wdtc" commands or during power on ; and reset to ?0? by wdt time-out (see section 6.5.2, the t and p status under status register for more details). bit 3 (p): power-down bit. set to ?1? during power-on or by a "wdtc" command and reset to ?0? by a "slep" command (see section 6.5.2, the t and p status under status register for more details). bit 2 (z): zero flag. set to "1" if the result of an arithmetic or logic operation is zero. bit 1 (dc): auxiliary carry flag bit 0 (c): carry flag 6.1.5 r4 (ram select register) bit 7: set to ?0? all the time bit 6: used to select bank 0 or bank 1 of register bits 5~0: used to select a register (address: 00~0f, 10~3f) in the indirect addressing mode see the table under section 6.1.3.1, data memory configuration for data memory configuration.
em78p259n/260n 8-bit microprocessor w i th otp rom 10 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) 6.1.6 r5 ~ r6 (port 5 ~ port 6) r5 & r6 are i/o registers the upper 2 bits of r5 are fixed to ?0? (if em78p259n is selected). only the lower 6 bits of r5 are available (this applies to em78p259n only as em78p260n can use all the bits) 6.1.7 r7 (port 7) bit 7 6 5 4 3 2 1 0 em78p259n/260n ?0? ?0? ?0? ?0? ?0? ?0? ?0? i/o ice259n c3 c2 c1 c0 rcm1 rcm0 ?0? i/o note r7 is an i/o register for em78p259n/260n, only the lower 1 bit of r7 is available. bit 7 ~ bit 2: [with em78p259n/260n]: unimplemented, read as ?0?. [with simulator (c3~c0, rcm1, & rcm0)]: are irc calibration bits in irc oscillator mode. under irc oscillator mode of ice259n simulator, these are the irc mode selection bits and irc calibration bits. bit 7 ~ bit 4 (c3 ~ c0): calibrator of internal rc mode c3 c2 c1 c0 frequency (mhz) 0 0 0 0 (1-36%) x f 0 0 0 1 (1-31.5%) x f 0 0 1 0 (1-27%) x f 0 0 1 1 (1-22.5%) x f 0 1 0 0 (1-18%) x f 0 1 0 1 (1-13.5%) x f 0 1 1 0 (1-9%) x f 0 1 1 1 (1-4.5%) x f 1 1 1 1 f (default) 1 1 1 0 (1+4.5%) x f 1 1 0 1 (1+9%) x f 1 1 0 0 (1+135%) x f 1 0 1 1 (1+18%) x f 1 0 1 0 (1+22.5%) x f 1 0 0 1 (1+27%) x f 1 0 0 0 (1+31.5%) x f 1. frequency values shown are theoretical and taken at an instance of a high frequency mode. hence, frequency values are shown for reference only. definite val ues depend on the actual process. 2. similar way of calculation is also applicable to low frequency mode.
em78p259n/260n 8-bit microprocessor w i th otp rom product specification (v1.0) 06.16.2005 ? 11 (this specification is subject to change without further notice) bit 3 & bit 2 ( rcm1, rcm0): irc mode selection bits rcm 1 rcm 0 frequency (mhz) 1 1 4 (default) 1 0 8 0 1 1 0 0 455khz 6.1.8 r8 (aisr: adc input select register) the aisr register defines the pins of port 5 as analog inputs or as digital i/o, individually. 7 6 5 4 3 2 1 0 ? ? ? ? ade3 ade2 ade1 ade0 bit 7 ~ bit 4: not used bit 3 (ade3 ): ad converter enable bit of p53 pin 0 = disable adc3, p53 acts as i/o pin 1 = enable adc3, acts as analog input pin bit 2 (ade2 ): ad converter enable bit of p52 pin 0 = disable adc2, p52 acts as i/o pin 1 = enable adc2, acts as analog input pin bit 1 (ade1 ): ad converter enable bit of p51 pin 0 = disable adc1, p51 acts as i/o pin 1 = enable adc1, acts as analog input pin bit 0 (ade0 ): ad converter enable bit of p50 pin. 0 = disable adc0, p50 acts as i/o pin 1 = enable adc0, acts as analog input pin
em78p259n/260n 8-bit microprocessor w i th otp rom 12 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) 6.1.9 r9 (adcon: adc control register) 7 6 5 4 3 2 1 0 vrefs c k r 1 c k r 0 adrun a d p d ? a d i s 1 a d i s 0 bit 7 (vrefs): the input source of the v r ef of the adc 0 = the v r ef of the adc is connec ted to vdd (default value), and the p54/vref pin carries out the function of p54 1 = the v r ef of the adc is connected to p54/vref note t he p54/t cc/ vref pin c a n n o t be a p p lie d t o t cc a nd vr ef at the sa me time. if p53/t cc/vref acts as vr ef analog in pu t pin, then cont bit 5 ?t s? mu st be ?0.? t he p54/t cc/vref pin priority is as follow s : p53/tcc/vref pin priority high me dium low vref tcc p54 bit 6 & bit 5 (ckr1 & ckr0): the prescaler of oscillator clock rate of adc 00 = 1 : 4 (default value) 01 = 1 : 16 10 = 1 : 64 11 = 1 : wdt ring oscillator frequency ckr0:ckr1 ope r a t ion mode ma x . ope r a t ion fre que nc y 00 fsco/4 1 mhz 01 fsco/16 4 mhz 10 fsco/64 16mhz 11 internal rc ? bit 4 (adrun): adc st art s to run. 1 = an ad conversion is st arted. this bit can be set by sof t ware 0 = reset upon completion of the conversion. this bit cannot be reset through sof t ware bit 3 (adpd): adc power-down mode 1 = adc is operating 0 = switch of f the resistor reference to save power even while the cpu is operating bit 2: not used
em78p259n/260n 8-bit microprocessor w i th otp rom product specification (v1.0) 06.16.2005 ? 13 (this specification is subject to change without further notice) bit 1 ~ bit 0 (adis1 ~adis0): analog input select 00 = adin0/p50 01 = adin1/p51 10 = adin2/p52 11 = adin3/p53 these bits can only be changed when the adif bit (see section 6.1.14, re (interrupt status 2 & wake-up control register) ) and the adrun bit are both low. 6.1.10 ra (adoc: adc offset calibration register) 7 6 5 4 3 2 1 0 cali sign vof[2] vof[1] vof[0] ?0? ?0? ?0? bit 7 (cali): calibration enable bit for adc offset 0 = calibration disable 1 = calibration enable bit 6 (sign): polarity bit of offset voltage 0 = negative voltage 1 = positive voltage bit 5 ~ bit 3 (vof[2] ~ vof[0]): offset voltage bits vof[2] vof[1] vof[0] em78p259n/260n ice259n 0 0 0 0lsb 0lsb 0 0 1 2lsb 1lsb 0 1 0 4lsb 2lsb 0 1 1 6lsb 3lsb 1 0 0 8lsb 4lsb 1 0 1 10lsb 5lsb 1 1 0 12lsb 6lsb 1 1 1 14lsb 7lsb bit 2 ~ bit 0: unimplemented, read as ?0? 6.1.11 rb (addata: converted value of adc) 7 6 5 4 3 2 1 0 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 when the ad conversion is completed, the result is loaded into the addata. the adrun bit is cleared, and the adif (see section 6.1.14, re (interrupt status 2 & wake-up control register) ) is set. rb is read only.
em78p259n/260n 8-bit microprocessor w i th otp rom 14 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) 6.1.12 rc (addata1h: converted value of adc) 7 6 5 4 3 2 1 0 ?0? ?0? ?0? ?0? ad11 ad10 ad9 ad8 when the ad conversion is completed, the result is loaded into the addata1h. the adrun bit is cleared, and the adif (see section 6.1.14, re (interrupt status 2 & wake-up control register) ) is set. rc is read only 6.1.13 rd (addata1l: converted value of adc) 7 6 5 4 3 2 1 0 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 when the ad conversion is completed, the result is loaded into the addata1l. the adrun bit is cleared, and the adif (see section 6.1.14, re (interrupt status 2 & wake-up control register) ) is set. rd is read only 6.1.14 re (interrupt status 2 & wake-up control register) 7 6 5 4 3 2 1 0 ? ? adif cmpif adwe cmpwe icwe - note re <5,4> can be cleared by instruction but cannot be set. ioce0 is the interrupt mask register. reading re will result to "logic and" of re and ioce0. bit 7 & bit 6: not used bit 5 (adif): interrupt flag for analog to digital conversion. set when ad conversion is completed. reset by software 0 = no interrupt occurs 1 = interrupt request bit 4 (cmpif): comparator interrupt flag. set w hen a change occurs in the output of comparator. reset by software. 0 = no interrupt occurs 1 = interrupt request bit 3 (adwe): adc wake-up enable bit 0 = disable adc wake-up 1 = enable adc wake-up when ad conversion enters sleep mode, this bit must be set to ?enable?.
em78p259n/260n 8-bit microprocessor w i th otp rom product specification (v1.0) 06.16.2005 ? 15 (this specification is subject to change without further notice) bit 2 (cmpwe): comparator wake-up enable bit 0 = disable comparator wake-up 1 = enable comparator wake-up when comparator enters sleep mode, this bit must be set to ?enable.? bit 1 (icwe): port 5 input change to wake-up status enable bit 0 = disable port 5 input change to wake-up status 1 = enable port 5 input change to wake-up status when port 5 change enters sleep mode, this bit must be set to ?enable.? bit 0: not implemented, read as ?0? 6.1.15 rf (interrupt status 2 register) 7 6 5 4 3 2 1 0 lpwtif hpwtif tcccif tccbif tccaif exif icif tcif note ?1? means interrupt request; ?0? means no interrupt occurs. rf can be cleared by instruction but cannot be set. iocf0 is the relative interrupt mask register. reading rf will result to "logic and" of rf and iocf0. bit 7 (lpwtif): internal low-pulse width timer underflow interrupt flag for ir/pwm function. reset by software. bit 6 (hpwtif): internal high-pulse width timer underflow interrupt flag for ir/pwm function. reset by software. bit 5 (tcccif): tccc overflow interrupt flag. se t when tccc overflows. reset by software. bit 4 (tccbif): tccb overflow interrupt flag. se t when tccc overflows. reset by software. bit 3 (tccaif): tcca overflow interrupt flag. set when tccc overflows. reset by software. bit 2 (exif): external interrupt flag. set by falling edge on /int pin. reset by software. bit 1 (icif): port 5 input status change interrupt flag. set when port 5 input changes. reset by software. bit 0 (tcif): tcc overflow interrupt flag. set when tcc overflows. reset by software. 6.1.16 r10 ~ r3f all of these are 8-bit general-purpose registers.
em78p259n/260n 8-bit microprocessor w i th otp rom 16 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) 6.2 special purpose registers 6.2.1 a (accumulator) internal data transfer, or instruction operand holding. it cannot be addressed. 6.2.2 cont (control register) 7 6 5 4 3 2 1 0 inte int ts te pste pst2 pst1 pst0 note the cont register is both readable and writable. bit 6 is read only. bit 7 (inte): int signal edge 0 = interrupt occurs at the rising edge on the int pin 1 = interrupt occurs at the falling edge on the int pin bit 6 (int): interrupt enable flag 0 = masked by disi or hardware interrupt 1 = enabled by the eni/reti instructions this bit is readable only. bit 5 (ts): tcc signal source 0 = internal instruction cycle clo ck. p54 is bi-directional i/o pin. 1 = transition on the tcc pin bit 4 (te): tcc signal edge 0 = increment if the transition from low to high takes place on the tcc pin 1 = increment if the transition from high to low takes place on the tcc pin. bit 3 (pste): prescaler enable bit for tcc 0 = prescaler disable bit. tcc rate is 1:1. 1 = prescaler enable bit. tcc rate is set as bit 2 ~ bit 0.
em78p259n/260n 8-bit microprocessor w i th otp rom product specification (v1.0) 06.16.2005 ? 17 (this specification is subject to change without further notice) bit 2 ~ bit 0 (pst2 ~ pst0): tcc prescaler bits pst2 pst1 pst0 tcc rate 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 note tcc timeout period [1/fosc x presca ler x 256 (tcc cnt) x 1 (clk=2)] tcc timeout period [1/fosc x presca ler x 256 (tcc cnt) x 2 (clk=4)] 6.2.3 ioc50 ~ ioc70 (i/o port control register) " 1 " puts the relative i/o pin into high impedance, while " 0 " defines the relative i/o pin as output. only the lower 6 bits of ioc50 can be defined (this applies to em78p259n only as em78p260n can use all the bits). only the lower 1 bits of ioc70 can be defined, the others bits are not available. ioc50 , ioc60 , and ioc70 registers are all readable and writable 6.2.4 ioc80 (comparator and tcca control register) 7 6 5 4 3 2 1 0 ? ? cmpout cos1 cos0 tccaen tccats tccate note bits 4 ~ 0 of the ioc80 regi ster are both r eadable and writable. bit5 of the ioc80 register is readable only. bit 7 & bit 6: not used bit 5 (cmpout): the result of the comparator output this bit is readable only
em78p259n/260n 8-bit microprocessor w i th otp rom 18 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) bit 4 & bit 3 (cos1 & cos0): comparator/op select bits cos1 cos0 function description 0 0 comparator and op not used. p64, p65, and p66 act as normal i/o pin 0 1 acts as comparator and p64 acts as normal i/o pin 1 0 acts as comparator and p64 acts as comparator output pin (co) 1 1 acts as op and p64 acts as op output pin (co) bit 2 (tccaen): tcca enable bit 0 = disable tcca 1 = enable tcca as a counter bit 1 (tccats): tcca signal source 0 =: internal instruction cycle cloc k. p61 is a bi-directional i/o pin. 1 = transit through the tcca pin bit 0 (tccate): tcca signal edge 0 = increment if transition from low to high takes place on the tcca pin 1 = increment if transition from high to low takes place on the tcca pin 6.2.5 ioc90 (tccb and tccc control register) 7 6 5 4 3 2 1 0 tccbhe tccben tccbts tccbte ? tcccen tcccts tcccte bit 7 (tccbhe): control bit is used to enable the mo st significant byte of counter 1 = enable the most signi ficant byte of tccbh tccb is a 16-bit counter 0 = disable the most significant byte of tccbh (default value) tccb is an 8-bit counter bit 6 (tccben): tccb enable bit 0 = disable tccb 1 = enable tccb as a counter bit 5 (tccbts) tccb signal source 0 = internal instruction cycle clock. p62 is a bi-directional i/o pin. 1 = transit through the tccb pin
em78p259n/260n 8-bit microprocessor w i th otp rom product specification (v1.0) 06.16.2005 ? 19 (this specification is subject to change without further notice) bit 4 (tccbte): tccb signal edge 0 = increment if the transition from low to high takes place on the tccb pin 1 = increment if the transition from high to low takes place on the tccb pin bit 3: not used. bit 2 (tcccen): tccc enable bit 0 = disable tccc 1 = enable tccc as a counter bit 1 (tcccts) tccc signal source 0 = internal instruction cycle clock. p63 is a bi-directional i/o pin. 1 = transit through the tccc pin bit 0 (tcccte): tccc signal edge 0 = increment if the transition from low to high takes place on the tccc pin 1 = increment if the transition from high to low takes place on the tccc pin 6.2.6 ioca0 (ir and tccc scale control register) 7 6 5 4 3 2 1 0 tcccse tcccs2 tcccs1 tcccs0 ire hf lgp iroute bit 7 (tcccse): scale enable bit for tccc an 8-bit counter is provided as scale for tccc and ir-mode. when in ir-mode, tccc counter scale uses the low-time segments of the pulse generated by fcarrier frequency modulation (see fig. 6-11 in section 6.8.2, function description ). 0 = scale disable bit, tccc rate is 1 : 1 1 = scale enable bit, tccc rate is set as bit 6 ~ bit 4
em78p259n/260n 8-bit microprocessor w i th otp rom 20 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) bit 6 ~ bit 4 (tcccs2 ~ tcccs0): tccc scale bits the tcccs2 ~ tcccs0 bits of t he ioca0 register are used to determine the scale ratio of tccc as shown below : tcccs2 tcccs1 tcccs0 tccc rate 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 bit 3 (ire): infrared remote enable bit 0 = disable ire, i.e., disable h/w modulator function. irout pin fixed to high level and the tccc is up counter. 1 = enable ire, i.e., enable h/w modulator function. pin 67 defined as irout. if hp=1, the tccc counter scale uses the low-time segments of the pulse generated by fcarrier frequency modulation (see fig. 6-11 in section 6.8.2, function description ). when hp=0, the tccc is up counter. bit 2 (hf): high frequency bit 0 = pwm application. irout waveform is achieved according to high-pulse width timer and low-pulse width timer which determine the high time width and low time width respectively 1 = ir application mode. the low-time segments of the pulse generated by fcarrier frequency modulation (see fig. 6-11 in section 6.8.2, function description ) bit 1 (lgp): long pulse. 0 = the high-time register and low-time register is valid 1 = the high-time register is ignored. a single pulse is generated bit 0 (iroute): control bit to define the p67 (irout) pin function 0 = p67 defined as bi-directional i/o pin 1 = p67 defined as irout. under this condition, the i/o control bit of p67 (bit 7 of ioc60) must be set to ?0?
em78p259n/260n 8-bit microprocessor w i th otp rom product specification (v1.0) 06.16.2005 ? 21 (this specification is subject to change without further notice) 6.2.7 iocb0 (pull-down control register) 7 6 5 4 3 2 1 0 /pd57 /pd56 /pd55 /pd54 /pd53 /pd52 /pd51 /pd50 note iocb0 register is both readable and writable bit 7 (/pd57): control bit is used to enable the pull-down of the p57 pin (applicable to em78p260n only) 0 = enable internal pull-down 1 = disable internal pull-down bit 6 (/pd56): control bit is used to enable the pull-down of the p56 pin (applicable to em78p260n only) bit 5 (/pd55): control bit is used to enable the pull-down of the p55 pin bit 4 (/pd54): control bit is used to enable the pull-down of the p54 pin bit 3 (/pd53): control bit is used to enable the pull-down of the p53 pin bit 2 (/pd52): control bit is used to enable the pull-down of the p52 pin bit 1 (/pd51): control bit is used to enable the pull-down of the p51 pin bit 0 (/pd50): control bit is used to enable the pull-down of the p50 pin. 6.2.8 iocc0 (open-drain control register) 7 6 5 4 3 2 1 0 /od67 /od66 /od65 /od64 /od63 /od62 /od61 /od60 note the iocc0 register is both readable and writable bit 7 (/od67): control bit is used to enable the open-drain of the p67 pin 0 = enable open-drain output 1 = disable open-drain output bit 6 (/od66): control bit is used to enable the open-drain of the p66 pin bit 5 (/od65): control bit is used to enable the open-drain of the p65 pin bit 4 (/od64): control bit is used to enable the open-drain of the p64 pin bit 3 (/od63): control bit is used to enable the open-drain of the p63 pin bit 2 (/od62): control bit is used to enable the open-drain of the p62 pin bit 1 (/od61): control bit is used to enable the open-drain of the p61 pin bit 0 (/od60): control bit is used to enable the open-drain of the p60 pin
em78p259n/260n 8-bit microprocessor w i th otp rom 22 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) 6.2.9 iocd0 (pull-high control register) 7 6 5 4 3 2 1 0 /ph57 /ph56 /ph55 /ph54 /ph53 /ph52 /ph51 /ph50 note the iocd0 register is both readable and writable bit 7 (/ph57): control bit is used to enable the pull-high of the p57 pin (applicable to em78p260n only). 0 = enable internal pull-high; 1 = disable internal pull-high. bit 6 (/ph56): control bit is used to enable the pull-high of the p56 pin (applicable to em78p260n only). bit 5 (/ph55): control bit is used to enable the pull-high of the p55 pin. bit 4 (/ph54): control bit is used to enable the pull-high of the p54 pin. bit 3 (/ph53): control bit is used to enable the pull-high of the p53 pin. bit 2 (/ph52): control bit is used to enable the pull-high of the p52 pin. bit 1 (/ph51): control bit is used to enable the pull-high of the p51 pin. bit 0 (/ph50): control bit is used to enable the pull-high of the p50 pin. 6.2.10 ioce0 (wdt control & interrupt mask registers 2) 7 6 5 4 3 2 1 0 wdte eis adie cmpie pswe psw2 psw1 psw0 bit 7 (wdte): control bit is used to enable watchdog timer 0 = disable wdt 1 = enable wdt wdte is both readable and writable bit 6 (eis): control bit is used to define the function of the p60 (/int) pin 0 = p60, bi-directional i/o pin 1 = /int, external interrupt pin. in this case, the i/o control bit of p60 (bit 0 of ioc60) must be set to "1" note when eis is "0," the path of /int is masked. when eis is "1," the status of /int pin can also be read by way of reading port 6 (r6). refer to fig. 6-3 (i/o port and i/o control register circuit for p60( /int)) under section 6.4 (i/o ports). eis is both readable and writable.
em78p259n/260n 8-bit microprocessor w i th otp rom product specification (v1.0) 06.16.2005 ? 23 (this specification is subject to change without further notice) bit 5 (adie): adif interrupt enable bit 0 = disable adif interrupt 1 = enable adif interrupt bit 4 (cmpie ) : cmpif interrupt enable bit. 0 = disable cmpif interrupt 1 = enable cmpif interrupt bit 3 (pswe): prescaler enable bit for wdt 0 = prescaler disable bit, wdt rate is 1:1 1 = prescaler enable bit, wdt rate is set as bit2 ~ bit0 bit 2 ~ bit 0 (psw2 ~ psw0): wdt prescaler bits psw2 psw1 psw0 wdt rate 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 6.2.11 iocf0 (interrupt mask register) 7 6 5 4 3 2 1 0 lpwtie hpwtie tcccie tccbie tccaie exie icie tcie note the iocf0 register is both readable and writable individual interrupt is enabled by setting its associated control bit in the iocf0 and in ioce0 bit 4 & 5 to "1". global interrupt is enabled by the eni instruction and is disabled by the disi instruction. refer to fig. 6-7 (interrupt input circuit) under secti on 6.6 (interrupt). bit 7 (lpwtie): lpwtif interrupt enable bit 0 = disable lpwtif interrupt 1 = enable lpwtif interrupt bit 6 (hpwtie): hpwtif interrupt enable bit 0 = disable hpwtif interrupt 1 = enable hpwtif interrupt
em78p259n/260n 8-bit microprocessor w i th otp rom 24 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) bit 5 (tcccie): tcccif interrupt enable bit 0 = disable tcccif interrupt 1 = enable tcccif interrupt bit 4 (tccbie): tccbif interrupt enable bit 0 = disable tccbif interrupt 1 = enable tccbif interrupt bit 3 (tccaie): tccaif interrupt enable bit 0 = disable tccaif interrupt 1 = enable tccaif interrupt bit 2 (exie): exif interrupt enable bit 0 = disable exif interrupt 1 = enable exif interrupt bit 1 (icie): icif interrupt enable bit 0 = disable icif interrupt 1 = enable icif interrupt bit 0 (tcie): tcif interrupt enable bit. 0 = disable tcif interrupt 1 = enable tcif interrupt 6.2.12 ioc51 (tcca counter) ioc51 (tcca) is an 8-bit clock counter. it can be read, written, and cleared on any reset condition and is an up counter. note tcca timeout period [1/fosc x (256-tcca cnt) x 1(clk=2)] tcca timeout period [1/fosc x (256-tcca cnt) x 2(clk=4)] 6.2.13 ioc61 (tccb counter) an 8-bit clock counter is for the least significant byte of tccbx (tccb) . it can be read, written, and cleared on any reset condition and is an up counter.
em78p259n/260n 8-bit microprocessor w i th otp rom product specification (v1.0) 06.16.2005 ? 25 (this specification is subject to change without further notice) 6.2.14 ioc71 (tccbh/msb counter) an 8-bit clock counter is for the most significant byte of tccbx (tccbh) . it can be read, written, and cleared on any reset condition. when tccbhe (ioc90) is ?0,? then tccbh is disabled. when tccbhe is?1,? then tccb is a 16-bit length counter. note when tccbh is disabled: tccb timeout period [1/fosc x ( 256 - tccb cnt ) x 1(clk=2)] tccb timeout period [1/fosc x ( 256 - tccb cnt ) x 2(clk=4)] when tccbh is enabled: tccb timeout period {1/fosc x [ 65536 - (tccbh * 256 + tccb cnt)] x 1(clk=2)} tccb timeout period {1/fosc x [ 65536 - (tccbh * 256 + tccb cnt)] x 2(clk=4)} 6.2.15 ioc81 (tccc counter) ioc81 (tccc) is an 8-bit clock counter that c an be extended to 16-bit counter. it can be read, written, and cleared on any reset condition. if hf (bit 2 of ioca0) = 1 and ire (bit 3 of ioca0) = 1, tccc counter scale uses the low-time segments of the pulse generated by fcarrier frequency modulation (see fig. 6-11 in section 6.8.2, function description ). then tccc value will be tccc predict value. when hp = 0 or ire = 0, the tccc is an up counter. note under tccc up counter mode: tccc timeout period [1/fosc x scaler (ioca0) x (256-tccc cnt) x 1(clk=2)] tccc timeout period [1/fosc x scaler (ioca0) x (256-tccc cnt) x 2(clk=4)] when hp = 1 and ire = 1, tccc counter scale uses the low-time segments of the pulse generated by fcarrier frequency modulation. note under ir mode: fcarrier = ft/ 2 { [1+decimal tccc count er value (ioc81)] * tccc scale (ioca0) } ft is system clock : ft = fosc/1 (clk=2) ft = fosc/2 (clk=4)
em78p259n/260n 8-bit microprocessor w i th otp rom 26 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) 6.2.16 ioc91 (low-time register) the 8-bit low-time register controls t he active or low segment of the pulse. the decimal value of its contents determi nes the number of oscillator cycles and verifies that the ir out pin is active. the active period of ir out can be calculated as follows : note low time width = { [1+decimal low-time value (ioc91)] * low time scale(iocb1) } / ft ft is system clock : ft = fosc/1 (clk=2) ft = fosc/2 (clk=4) when an interrupt is generated by the low time down counter underflow (when enabled), the next instruction will be fetc hed from address 015h (low time). 6.2.17 ioca1 (high time register) the 8-bit high-time register controls t he inactive or high period of the pulse. the decimal value of its contents determi nes the number of oscillator cycles and verifies that the ir out pin is inactive. t he inactive period of ir out can be calculated as follows : note high time width = {[1+decimal high-time value (ioca1)] * high time scale(iocb1) } / ft ft is system clock : ft=fosc/1(clk=2) ft=fosc/2(clk=4) when an interrupt is generated by the high time down counter underflow (when enabled), the next instruction will be fetched from address 012h (high time). 6.2.18 iocb1 high/low time scale control register) 7 6 5 4 3 2 1 0 htse hts2 hts1 hts0 ltse lts2 lts1 lts0 bit 7 (htse): high-time scale enable bit. 0 = scale disable bit, high-time rate is 1 : 1 1 = scale enable bit, high-time rate is set as bit 6~bit 4.
em78p259n/260n 8-bit microprocessor w i th otp rom product specification (v1.0) 06.16.2005 ? 27 (this specification is subject to change without further notice) bit 6 ~ bit 4 (hts2 ~ hts0): high-time scale bits : hts2 hts1 hts0 high-time rate 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 bit 3 (ltse): low-time scale enable bit. 0 = scale disable bit, low-time rate is 1:1 1 = scale enable bit, low-time rate is set as bit 2~bit 0. bit 2 ~ bit 0 (lts2 ~ lts0): low-time scale bits : lts2 lts1 lts0 low-time rate 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 6.2.19 iocc1 (tcc prescaler counter) tcc prescaler counter can be read and written : pst2 pst1 pst0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tcc rate 0 0 0 - - - - - - - v 1:2 0 0 1 - - - - - - v v 1:4 0 1 0 - - - - - v v v 1:8 0 1 1 - - - - v v v v 1:16 1 0 0 - - - v v v v v 1:32 1 0 1 - - v v v v v v 1:64 1 1 0 - v v v v v v v 1:128 1 1 1 v v v v v v v v 1:256 v = valid value the tcc prescaler counter is assigned to tcc (r1). the contents of the iocc1 register ar e cleared when one of the following occurs : a value is written to tcc register a value is written to tcc presca ler bits (bit 3,2,1,0 of cont) power on reset, /reset wdt time out reset
em78p259n/260n 8-bit microprocessor w i th otp rom 28 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) 6.3 tcc/wdt and prescaler there are two 8-bit counters available as prescalers that can be extended to 16-bit counter for the tcc and wdt respectively. the pst2 ~ pst0 bits of the cont register are used to determine the ratio of the tcc prescaler, and the pwr2 ~ pwr0 bits of the ioce0 register are used to det ermine the wdt prescaler. the prescaler counter is cleared by the instructions each time such instructions are written into tcc. the wdt and prescaler will be cleared by the ?wdtc? and ?slep? instructions. fig. 6-1 (next page) depicts the block diagram of tcc/wdt. tcc (r1) is an 8-bit timer/counter. the tcc clock source can be internal clock or external signal input (edge selectable from the tcc pin). if tcc signal source is from internal clock, tcc will increase by 1 at every instruction cycle (without prescaler). referring to fig. 6-1, clk=fosc/2 or cl k=fosc/4 is dependent to the code option bit . clk=fosc/2 if the clks bit is "0," and clk=fosc/4 if the clks bit is "1." if tcc signal source is from external clock input, tcc will increase by 1 at every falling edge or rising edge of the tcc pin. tcc pin input time length (kept in high or low level) must be greater than 1clk. note the internal tcc will stop running when sl eep mode occurs. however, during ad conversion, when tcc is set to ?slep? instruction, if the adwe bit of the re register is enabled, the tcc will keep on running the watchdog timer is a free running on-chip rc oscillator. the wdt will keep on running even when the oscillator driver has been turned off (i.e., in sleep mode). during normal operation or sleep mode, a wd t time-out (if enabled) will cause the device to reset. the wdt can be enabled or disabled at any time during normal mode through software programming. refer to wd te bit of ioce0 register (section 6.2.10 ioce0 (wdt control & interrupt mask registers 2) . with no prescaler, the wdt time-out period is approximately 18ms 1 or or 4.5ms 2 . vdd=5v, wdt time-out period = 16.5ms 30% vdd=3v, wdt time-out period = 18ms 30% 5v, wdt time-out period = 4.2ms 30% vdd=3v, wdt time-out period = 4.5ms 30% 1 2 vdd=
em78p259n/260n 8-bit microprocessor w i th otp rom produc t spe c i fic a t ion (v1.0) 06.16.2 005 ? 29 (this specification is subject to change without further notice) 8 - b i t c o u n te r wd t p r es cal e r 8 t o 1 m u x w d t ti m e o u t wd t e (i o c e 0 ) t cc p i n mu x c l k ( f os c / 2 or f o s c / 4 ) 8- b i t c ount e r ( i o c c 1 ) 8 t o 1 m u x te ( c o n t ) da t a b u s t c c over f l ow in te r r u p t ts ( c o n t) s ync 2 cy cl es t cc ( r 1 ) 0 1 psw 2 ~ 0 (i o c e 0 ) p r es cal er psr 2 ~ 0 ( c ont ) f i g. 6-1 t cc and w d t block diagram 6.4 i/o port s the i/o regi sters (port 5, port 6, and port 7) are bi-direction al tri-state i/o ports. port 5 is pulled-high and pulled-down internally by software. likewise, p6 has its open-drain output throu g h softwa r e. port 5 feature s an input statu s cha nge d interrupt (or wa ke-up ) function. each i/o pin can be defined as "input" or "output" pin by the i/o control register (ioc5 ~ ioc7). the i/o regist ers and i/o control registers are both readable and writable. the i/o interface circuits for port 5, port 6, and port7 are illustrated in figures 6-2, 6-3, 6-4, & 6-5 (see next page).
em78p259n/260n 8-bit microprocessor w i th otp rom 30 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) pc w r pcrd pd w r pdrd iod 0 1 m u x po rt q q _ d d q q _ cl k p r c l cl k p r c l note: open-drain is not show n in the figure. fig. 6-2 i/o port and i/o control regi ster circuit for port 6 and port7 p crd io d pc w r pd w r p drd bi t 6 o f io ce po r t m u x 0 1 clk clk clk p p p r r r c l l l c c q q q q q q d d d _ _ _ in t note : open-drain is not show n in the figure. fig. 6-3 i/o port and i/o control register circuit for p60 (/int)
em78p259n/260n 8-bit microprocessor w i th otp rom produc t spe c i fic a t ion (v1.0) 06.16.2 005 ? 31 (this specification is subject to change without further notice) pcrd m u x iod 0 1 pdrd p50 ~ p57 pcwr d q q @ clk 1 3 $ - pdwr d q q @ clk 1 3 $ - 1 3 $ - clk dq q @ ti n port note : pull-high (dow n) is not show n in the figure. fig. 6-4 i/o port and i/o control register circuit for port 50 ~ p57 ti 1 ti 8 io c f . 1 ti 0 rf . 1 ?. f i g. 6-5 port 5 block diagram w i th input change interrupt/w ake-up
em78p259n/260n 8-bit microprocessor w i th otp rom 32 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) 6.4.1 usage of port 5 input change wake-up/interrupt function (1) wake-up (2) wake-up and interrupt (a) before sleep (a) before sleep 1. disable wdt 1. disable wdt 2. read i/o port 5 (mov r5,r5) 2. read i/o port 5 (mov r5,r5) 3. execute "eni" or "disi" 3. execute "eni" or "disi" 4. enable wake-up bit (set re icwe =1) 4. enable wake-up bit (set re icwe =1) 5. execute "slep" instruction 5. enable interrupt (set iocf0 icie =1) (b) after wake-up 6. execute "slep" instruction next instruction (b) after wake-up 1. if "eni" interrupt vector (006h) 2. if "disi" next instruction (3) interrupt (a) before port 5 pin change 1. read i/o port 5 (mov r5,r5) 2. execute "eni" or "disi" 3. enable interrupt (set iocf0 icie =1) (b) after port 5 pin changed (interrupt) 1. if "eni" interrupt vector (006h) 2. if "disi" next instruction 6.5 reset and wake-up 6.5.1 reset and wake-up operation a reset is initiated by one of the following events : 1. power-on reset 2. /reset pin input "low" 3. wdt time-out (if enabled). the device is kept under reset conditi on for a period of approximately 18ms 3 (except in lxt mode) after the reset is detected. wh en in lxt mode, the reset time is 500ms. two choices (18ms 3 or 4.5ms 4 ) are available for wdt-time out period . once reset occurs, the following functions are performed (the initial address is 000h) : the oscillator continues running, or will be started (if under sleep mode) the program counter (r2) is set to all "0" vdd=5v, wdt time-out period = 16.5ms 30%. vdd=3v, wdt time-out period = 18ms 30%. 5v, wdt time-out period = 4.2ms 30%. vdd=3v, wdt time-out period = 4.5ms 30%. 3 4 vdd=
em78p259n/260n 8-bit microprocessor w i th otp rom product specification (v1.0) 06.16.2005 ? 33 (this specification is subject to change without further notice) all i/o port pins are configured as input mode (high-impedance state) the watchdog timer and prescaler are cleared when power is switched on, the upper 3 bits of r3 is cleared the cont register bits are set to all "1" except for bit 6 (int flag) the iocb0 register bits are set to all "1" the iocc0 register bits are set to all "1" the iocd0 register bits are set to all "1" bits 7, 5, and 4 of ioce0 register is cleared bit 5 and 4 of re register is cleared rf and iocf0 registers are cleared executing the ?slep? instruction will asse rt the sleep (power down) mode. while entering into sleep mode, the oscillator, tcc, tcca, tccb, and tccc are stopped. the wdt (if enabled) is cleared but keeps on running. during ad conversion, when ?slep? instru ction i set; the oscillator, tcc, tcca, tccb, and tccc keep on running. the wdt (if enabled) is cleared but keeps on running. the controller can be awakened by: case 1 external reset input on /reset pin case 2 wdt time-out (if enabled) case 3 port 5 input status changes (if icwe is enabled) case 4 comparator output status changes (if cmpwe is enabled) case 5 ad conversion completed (if adwe enable) the first two cases (1 & 2) will cause the em78p260n to reset. the t and p flags of r3 can be used to determine the source of the reset (wake-up). cases 3, 4, & 5 are considered the continuation of program exec ution and the global interrupt ("eni" or "disi" being executed) decides whether or not the controller branches to the interrupt vector following wake-up. if eni is execut ed before slep, the instruction will begin to execute from address 0x06 (case 3), 0x0f (c ase 4), and 0x0c (case 5) after wake-up. if disi is executed before slep, the executi on will restart from the instruction next to slep after wake-up. only one of cases 1 to 5 can be enabled before entering into sleep mode. that is : case [a] if wdt is enabled before slep, all of the re bit is disabled. hence, the em78p259n/260n can be awakened only with case 1 or case 2. refer to the section on interrupt (section 6.6 below) for further details. case [b] if port 5 input status change is used to wake -up em78p259n/260n and the icwe bit of re register is enabled before slep, wdt must be disabled. hence, the em78p259n/260n can be awakened only with case 3. wake-up time is dependent on oscillator mode. under rc mode the reset time is 32 clocks (for oscillator stables). in high xtal mode, reset time is 2ms and 32clocks (for oscillator stables) ; and in low xtal mode, the reset time is 500ms.
em78p259n/260n 8-bit microprocessor w i th otp rom 34 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) case [c] if comparator output status change is used to wake-up the em78p259n/ 260n and cmpwe bit of the re register is enabled before slep, wdt must be disabled by software. hence, the em78p259n/260n can be awakened only with case 4. wake-up time is dependent on oscillator mode. under rc mode the reset time is 32 clocks (for oscillator stables). in high xtal mode, reset time is 2ms and 32clocks (for oscillator stables); and in low xtal mode, the reset time is 500ms. case [d] if ad conversion completed is used to wake-up the em78p259n/260n and adwe bit of re register is enabled before slep, wdt must be disabled by software. hence, the em78p259n/260n can be awakened only with case 5. the wake-up time is 15 tad (adc clock period). if port 5 input status change interrupt is used to wake up the em78p259n/260n (as in case [b] above), the following instruct ions must be executed before slep: bc r3, 7 ; select segment 0 mov a, @00xx1110b ; select wdt prescaler and disable wdt iow ioce0 wdtc ; clear wdt and prescaler mov r5, r5 ; read port 5 eni (or disi) ; enable (or disable) global interrupt mov a, @xxxxxx1xb ; enable port 5 input change wake-up bit mov re mov a, @xxxxxx1xb ; enable port 5 input change interrupt iow iocf0 slep ; sleep similarly, if the comparator interrupt is used to wake up the em78p259n/260n (as in case [c] above), the following instruct ions must be executed before slep: bc r3, 7 ; select segment 0 mov a, @xxx10xxxb ; select a comparator and p64 act as co pin iow ioc80 mov a, @00x11110b ; select wdt prescaler and disable wdt, and enable comparator output status change interrupt iow ioce0 wdtc ; clear wdt and prescaler eni (or disi) ; enable (or disable) global interrupt mov a, @xxx0x1xxb ; enable comparator output status change wake-up bit mov re slep ; sleep
em78p259n/260n 8-bit microprocessor w i th otp rom product specification (v1.0) 06.16.2005 ? 35 (this specification is subject to change without further notice) 6.5.1.1 wake-up and interrupt modes operation summary all categories under wake-up and interrupt modes are summarized below. signal sleep mode normal mode disi + iocf0 (exie) bit2=1 next instruction + set rf (exif)=1 eni + iocf0 (exie) bit2=1 int pin n/a interrupt vector (003h) + set rf (exif)=1 re (icwe) bit1=0, iocf0 (icie) bit1=0 iocf0 (icie) bit1=0 oscillator, tcc, tccx and ir/pwm are stopped. port5 input status changed wake-up is invalid. port5 input status change interrupted is invalid re (icwe) bit1=0, iocf0 (icie) bit1=1 n/a set rf (icif)=1, oscillator, tcc, tccx and ir/pwm are stopped. port5 input status changed wake-up is invalid. n/a re (icwe) bit1=1, iocf0 (icie) bit1=0 n/a wake-up + next instruction oscillator, tcc, tccx and ir/pwm are stopped. n/a re (icwe) bit1=1, disi + iocf0 (icie) bit1=1 disi + iocf0 (icie) bit1=1 wake-up + next instruction + set rf (icif)=1 oscillator, tcc, tccx and ir/pwm are stopped. next instruction + set rf (icif)=1 re (icwe) bit1=1, eni + iocf0 (icie) bit1=1 eni + iocf0 (icie) bit1=1 port5 input status change wake-up + interrupt vector (006h) + set rf (icif)=1 oscillator, tcc, tccx and ir/pwm are stopped. interrupt vector(006h)+ set rf (icif)=1 disi + iocf0 (tcie) bit0=1 next instruction + set rf (tcif)=1 eni + iocf0 (tcie) bit0=1 tcc over flow n/a interrupt vector (009h) + set rf (tcif)=1 re (adwe) bit3=0, ioce0 (adie) bit5=0 ioce0 (adie) bit5=0 clear r9 (adrun)=0, adc is stopped, ad conversion wake-up is invalid. oscillator, tcc, tccx and ir/pwm are stopped. ad conversion interrupted is invalid re (adwe) bit3=0, ioce0 (adie) bit5=1 n/a set rf (adif)=1, r9 (adrun)=0, adc is stopped, ad conversion wake-up is invalid. oscillator, tcc, tccx and ir/pwm are stopped. n/a re (adwe) bit3=1, ioce0 (adie) bit5=0 n/a wake-up + next instruction, oscillator, tcc, tccx and ir/pwm keep on running. wake-up when adc completed. n/a re (adwe) bit3=1, disi + ioce0 (adie) bit5=1 disi + ioce0 (adie) bit5=1 wake-up + next instruction + re (adif)=1, oscillator, tcc, tccx and ir/pwm keep on running. wake-up when adc completed. next instruction + re (adif)=1 re (adwe) bit3=1, eni + ioce0 (adie) bit5=1 eni + ioce0 (adie) bit5=1 ad conversion wake-up + interrupt vector (00ch)+ re (adif)=1, oscillator, tcc, tccx and ir/pwm keep on running. wake-up when adc completed. interrupt vector (00ch) + set re (adif)=1
em78p259n/260n 8-bit microprocessor w i th otp rom 36 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) re (cmpwe) bit2=0, ioce0 (cmpie) bit4=0 iocf0 (cmpie) bit4=0 comparator output status changed wake-up is invalid. oscillator, tcc, tccx and ir/pwm are stopped. comparator output status change interrupted is invalid. re (cmpwe) bit2=0, ioce0 (cmpie) bit4=1 n/a set re (cmpif)=1, comparator output status changed wake-up is invalid. oscillator, tcc, tccx and ir/pwm are stopped. n/a re (cmpwe) bit2=1, ioce0 (cmpie) bit4=0 n/a wake-up + next instruction, oscillator, tcc, tccx and ir/pwm are stopped. n/a re (cmpwe) bit2=1, disi + ioce0 (cmpie) bit4=1 disi + ioce0 (cmpie) bit4=1 wake-up + next instruction + set re (cmpif)=1, oscillator, tcc, tccx and ir/pwm are stopped. next instruction + set re (cmpif)=1 re (cmpwe) bit2=1, eni + ioce0 (cmpie) bit4=1 eni + ioce0 (cmpie) bit4=1 comparator (comparator output status change) wake-up + interrupt vector (00fh) + set re (cmpif)=1,oscillator, tcc, tccx and ir/pwm are stopped. interrupt vector (00fh) + set re (cmpif)=1 disi + iocf0 (hpwtif) bit6=1 next instruction + set rf (hpwtie)=1 eni + iocf0 (hpwtif) bit6 =1 ir/pwm underflow interrupt (high-pulse width timer underflow interrupt) n/a interrupt vector (012h) + set rf (hpwtie)=1 disi + iocf0 (lpwtif) bit7=1 next instruction + set rf (lpwtie)=1 eni + iocf0 (lpwtif) bit7 =1 ir/pwm underflow interrupt (low-pulse width timer underflow interrupt) n/a interrupt vector (015h) + set rf (lpwtie)=1 disi + iocf0 (tccaie) bit3=1 next instruction + set rf (tccaif)=1 eni + iocf0 (tccaie) bit3=1 tcca over flow n/a interrupt vector (018h) + set rf (tccaif)=1 disi + iocf0 (tccbie) bit4=1 next instruction + set rf (tccbif)=1 eni + iocf0 (tccbie) bit4=1 tccb over flow n/a interrupt vector (01bh) + set rf (tccbif)=1 disi + iocf0 (tcccie) bit5=1 next instruction + set rf (tcccif)=1 eni + iocf0 (tcccie) bit5=1 tccc over flow n/a interrupt vector (01eh) + set rf (tcccif)=1 wdt time out ioce (wdte) bit7=1 wake-up + reset (address 0x 00) reset (address 0x00)
em78p259n/260n 8-bit microprocessor w i th otp rom product specification (v1.0) 06.16.2005 ? 37 (this specification is subject to change without further notice) 6.5.1.2 register initial values after reset the following summarizes the initialized values for registers. address name reset type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit name c57 c56 c55 c54 c53 c52 c51 c50 type 259 n 260 n 259 n 260 n ? ? ? ? ? ? power-on 0 1 0 1 1 1 1 1 1 1 /reset and wdt 0 1 0 1 1 1 1 1 1 1 n/a ioc50 wake-up from pin change 0 p 0 p p p p p p p bit name c67 c66 c65 c64 c63 c62 c61 c60 power-on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 n/a ioc60 wake-up from pin change p p p p p p p p bit name x x x x x x x c70 power-on 0 0 0 0 0 0 0 1 /reset and wdt 0 0 0 0 0 0 0 1 n/a ioc70 wake-up from pin change p p p p p p p p bit name x x cmpout cos1 cos0 tccaen tccats tccate power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 n/a ioc80 wake-up from pin change p p p p p p p p bit name tccbhe tccben tccbts tccbte x tcccen t cccts t cccte power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 n/a ioc90 wake-up from pin change p p p p p p p p bit name tcccse tcccs2 tcccs1 tcccs0 ire hf lgp iroute power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 n/a ioca0 (ir cr) wake-up from pin change p p p p p p p p bit name /pd57 /pd56 /pd55 /pd54 /pd53 /pd52 /pd51 /pd50 power-on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 n/a iocb0 (pdcr) wake-up from pin change p p p p p p p p bit name /od67 /od66 /od65 /od64 /od63 /od62 /od61 /od60 power-on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 n/a iocc0 (odcr) wake-up from pin change p p p p p p p p
em78p259n/260n 8-bit microprocessor w i th otp rom 38 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) address name reset type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit name /ph57 /ph56 /ph55 /ph54 /ph53 /ph52 /ph51 /ph50 power-on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 n/a iocd0 (phcr) wake-up from pin change p p p p p p p p bit name wdtc eis adie cmpie pswe psw2 psw1 psw0 power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 n/a ioce0 wake-up from pin change p p p p p p p p bit name lpwtie hpwtie tcccie tccbie tccaie exie icie tcie power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 n/a iocf0 wake-up from pin change p p p p p p p p bit name tcca7 tcca6 tcca5 tcca4 tcca3 tcca2 tcca1 tcca0 power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 n/a ioc51 (tcca) wake-up from pin change p p p p p p p p bit name tccb7 tccb6 tccb5 tccb4 tccb3 tccb2 tccb1 tccb0 power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 n/a ioc61 (tccb) wake-up from pin change p p p p p p p p bit name tccbh7 tccbh6 tccbh5 tccb h4 tccbh3 tccbh2 tccbh1 tccbh0 power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 n/a ioc71 (tccbh) wake-up from pin change p p p p p p p p bit name tccc7 tccc6 tccc5 tccc4 tccc3 tccc2 tccc1 tccc0 power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 n/a ioc81 (tccc) wake-up from pin change p p p p p p p p bit name ltr7 ltr6 ltr5 ltr4 ltr3 ltr2 ltr1 ltr0 power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 n/a ioc91 (ltr) wake-up from pin change p p p p p p p p
em78p259n/260n 8-bit microprocessor w i th otp rom product specification (v1.0) 06.16.2005 ? 39 (this specification is subject to change without further notice) address name reset type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit name htr7 htr6 htr5 htr4 htr3 htr2 htr1 htr0 power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 n/a ioca1 (htr) wake-up from pin change p p p p p p p p bit name htse hts2 hts1 ht s0 ltse lts2 lts1 lts0 power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 n/a iocb1 (hlts) wake-up from pin change p p p p p p p p bit name tccpc7 tccpc6 tccpc5 tccp c4 tccpc3 tccpc2 tccpc1 tccpc0 power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 n/a iocc1 (tccpc) wake-up from pin change p p p p p p p p bit name inte int ts te pste pst2 pst1 pst0 power-on 1 0 1 1 0 0 0 0 /reset and wdt 1 0 1 1 0 0 0 0 n/a cont wake-up from pin change p p p p p p p p bit name ? ? ? ? ? ? ? ? power-on u u u u u u u u /reset and wdt p p p p p p p p 0x00 r0(iar) wake-up from pin change p p p p p p p p bit name ? ? ? ? ? ? ? ? power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 00 0 0x01 r1(tcc) wake-up from pin change p p p p p p p p bit name ? ? ? ? ? ? ? ? power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x02 r2(pc) wake-up from pin change jump to address 0x06 or continue to execute next instruction bit name rst iocs ps0 t p z dc c power-on 0 0 0 1 1 u u u /reset and wdt 0 0 0 t t p p p 0x03 r3(sr) wake-up from pin change p p p t t p p p
em78p259n/260n 8-bit microprocessor w i th otp rom 40 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) address name reset type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit name x bs x x x x x x power-on 0 0 u u u u u u /reset and wdt 0 0 p p p p p p 0x04 r4(rsr) wake-up from pin change 0 p p p p p p p bit name p57 p56 p55 p54 p53 p52 p51 p50 power-on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 0x05 r5 wake-up from pin change p p p p p p p p bit name p67 p66 p65 p64 p63 p62 p61 p60 power-on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 0x06 r6 wake-up from pin change p p p p p p p p bit name ? ? ? ? ? ? ? p70 power-on 0 0 0 0 0 0 0 1 /reset and wdt 0 0 0 0 0 0 0 1 0x7 r7 wake-up from pin change p p p p p p p p bit name ? ? ? ? ade3 ade2 ade1 ade0 power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x8 r8 (aisr) wake-up from pin change 0 0 0 0 p p p p bit name vrefs ckr1 ckr0 adrun adpd ? adis1 adis0 power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x9 r9 (adcon) wake-up from pin change p p p p p 0 p p bit name cali sign vof[2] vof[1] vof[0] ? ? ? power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0xa ra (adoc) wake-up from pin change p p p p p p p p bit name ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 power-on u u u u u u u u /reset and wdt u u u u u u u u 0xb rb (addata) wake-up from pin change p p p p p p p p
em78p259n/260n 8-bit microprocessor w i th otp rom produc t spe c i fic a t ion (v1.0) 06.16.2 005 ? 41 (this specification is subject to change without further notice) a d d r ess name reset t y p e bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bi t n a m e ? 0 ? ? 0 ? ? 0 ? ? 0 ? ad11 a d 1 0 a d 9 a d 8 pow e r - o n 0 0 0 0 u u u u /reset and wdt 0 0 0 0 u u u u 0xc rc (addata1h) wake-up from pin change 0 0 0 0 p p p p bit n a m e a d 7 a d 6 a d 5 a d 4 a d 3 a d 2 a d 1 a d 0 pow e r - o n u u u u u u u u /reset a n d w d t u u u u u u u u 0xd rd (addata1l0) wake-up from pin change p p p p p p p p bit name ?- ? adif cmpif a dwe c mpwe icwe ? pow e r - o n 0 0 0 0 0 0 0 0 /reset a n d w d t 0 0 0 0 0 0 0 0 0xe re (isr2) wake-up from pin change p p p p p p p p bit n a m e lpwtif hpwtif tcccif t ccbif tccaif e x i f i c i f t c i f pow e r - o n 0 0 0 0 0 0 0 0 /reset a n d w d t 0 0 0 0 0 0 0 0 0xf rf (isr1) wake-up from pin change p p p p p p p p b i t n a m e ? ? ? ? ? ? ? ? pow e r - o n u u u u u u u u /reset a n d w d t p p p p p p p p 0 x 1 0 ~ 0 x 3 f r 1 0 ~ r 3 f wake-up from pin change p p p p p p p p legend : x: not used u: unknow n or don?t care. p: previous value before reset t: check table under section 6.5.2 6.5.1.3 controller reset block diagram wd t tim e o u t os cillat or d q clk clr wdt vdd se tu p tim e res e t clk /rese t power-o n r e set v o lt age d e t ect or en w d t b f i g. 6-6 controller reset block diagram
em78p259n/260n 8-bit microprocessor w i th otp rom 42 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) 6.5.2 the t and p status under status (r3) register a reset condition is initiated by one of the following events : 1. power-on reset 2. /reset pin input "low" 3. wdt time-out (if enabled). the values of rst, t, and p as listed in the table below, are used to check how the processor wakes up. reset type rst t p power-on 0 1 1 /reset during operating mode 0 * p * p /reset wake-up during sleep mode 0 1 0 wdt during operating mode 0 0 1 wdt wake-up during sleep mode 0 0 0 wake-up on pin change during sleep mode 1 1 0 * p : previous status before reset the following shows the events that ma y affect the status of t and p. event rst t p power-on 0 1 1 wdtc instruction * p 1 1 wdt time-out 0 0 * p slep instruction * p 1 0 wake-up on pin changed during sleep mode 1 1 0 * p: previous value before reset 6.6 interrupt the em78p259n/260n has six interrupts as listed below : 1. tcc, tcca, tccb, tccc overflow interrupt 2. port 5 input status change interrupt 3. external interrupt [(p60, /int) pin] 4. analog to digital conversion completed 5. ir/pwm underflow interrupt 6. when the comparators status changes before the port 5 input status change inte rrupt is enabled, reading port 5 (e.g. "mov r5,r5") is necessary. each po rt 5 pin will have this feature if its status changes. the port 5 input status change interrupt w ill wake-up the em78p259n/260n from the sleep mode if it is enabled prior to going into the sleep mode by executing slep instruction. when wake-up occurs, the c ontroller will continue to execute program in-line if the global interrupt is disabled. if enabled, the global interrupt will branch out to the interrupt vector 006h.
em78p259n/260n 8-bit microprocessor w i th otp rom product specification (v1.0) 06.16.2005 ? 43 (this specification is subject to change without further notice) external interrupt equipped with digital noise rejection circuit (input pulse less than 8 system clocks time) is eliminated as noise. however, under low xtal oscillator (lxt) mode the noise rejection circuit will be disabl ed. edge selection is possible with inte of cont. when an interrupt is generated by the external interrupt (when enabled), the next instruction will be fetched from address 003h. refer to the word 1 bits 9 & 8 (section 6.14.2, code option register (word1)) for digital noise rejection definition rf and re are the interrupt status register that records the interrupt requests in the relative flags/bits. iocf0 and ioce0 are interrupt mask registers. the global interrupt is enabled by the eni instruction and is disabled by the disi instruction. once in the interrupt service routine, t he source of an interrupt can be determined by polling the flag bits in rf. the interrupt flag bit must be cleared by instructi ons before leaving the interrupt service routine to avoid recursive interrupts. the flag (except for the icif bit) in the interru pt status register (rf) is set regardless of the eni execution. note that the result of rf will be the logic and of rf and iocf0 (refer to figure below). the reti instruct ion ends the interrupt routine and enables the global interrupt (the eni execution). when an interrupt is generated by the ti mer clock/counter (when enabled), the next instruction will be fetched from address 009, 018, 01b , and 01eh (tcc, tcca, tccb, and tccc respectively). when an interrupt generated by the ad c onversion is completed (when enabled), the next instruction will be fetched from address 00ch. when an interrupt is generated by the high time / low time down counter underflow (when enabled), the next instruction will be fetched from address 012 and 015h (high time and low time respectively). when an interrupt is generated by t he comparators (when enabled), the next instruction will be fetched from address) 00fh (comparator interrupt). before the interrupt subroutine is execut ed, the contents of acc and the r3 and r4 registers will be saved by the hardware. if another interrupt occurs, the acc, r3, and r4 will be replaced by the new interrupt. afte r the interrupt service routine is completed, the acc, r3, and r4 registers are restored.
em78p259n/260n 8-bit microprocessor w i th otp rom 44 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) in t en i / di s i io d rf w r io c f r d io c f w r ir q n ir q m rf r d io c f / r es et /ir q n vc c rf cl k clk q q d p r l c _ p r l c q q _ d f i g. 6.7 interrupt input circuit i n t errupt s o urces int e r r upt o c cu rs eni/d i si s t ackac c s t ackr3 reti ac c r3 r4 stac k r 4 f i g. 6.8 interrupt backup diagram in em78p259 n/260 n, each individual i n terrupt so urce ha s its own interru pt vector a s depicted in the table below. interrupt vector interrupt status priority * 0 0 3 h e x t e r n a l i n t e r r u p t 1 006h port 5 pin change 2 009h t cc overflow interrupt 3 00ch ad conversion complete interrupt 4 00f h c o m p a r a t o r i n t e r r u p t 5 012h high-pulse w i dth timer underflow interrupt 6 015h low -pulse w i dth timer underflow interrupt 7 018h t cca overflow interrupt 8 01bh t ccb overflow interrupt 9 01eh t ccc overflow interrupt 10 * priority : 1 = highest ; 10 = low e st priority
em78p259n/260n 8-bit microprocessor w i th otp rom produc t spe c i fic a t ion (v1.0) 06.16.2 005 ? 45 (this specification is subject to change without further notice) 6.7 analog-t o -digit al converter (adc) the analog-to-digit al circuitry consist of a 4-bit analog multiplexer; three control registers (aisr/r8, adcon/r9, & adoc/r a), three dat a registers (adda t a /rb, adda t a 1 h /rc, & ad da t a 1l/rd ), and an adc with 12-bit resoluti on as sh ow n in th e functional block diagram below . the analog reference volt age (v ref) and the analog ground are connected via sep a rate input pins. the adc module utilizes successive approx imation to convert the unknown analog signal into a digit a l value. the result is fed to the adda t a , adda t a 1h, and adda t a 1l. input channels are selected by the analog input multiplexer via the adcon register bit s adis1 and adis0. addata1 h data bus ad c3 ad c2 ad c1 ad c0 vr e f po wer - do wn fs c o in te r n al r c 4-1 mu x 7 ~ 0 3 4 ad c ( s u cc es s i ve a p p r oxi mati on ) 3 5 6 adcon r f ais r adcon sta r t to c o nv e r t 0 1 adco n " o b m p h 4 x j u d i 0 1 2 3 4 5 6 7 8 9 10 11 addata1 l f i g. 6-9 analog-to-digit al conversion f unctional block diagram 6.7.1 adc control register (aisr/r8, adcon/r9, adoc/ra) 6.7.1.1 r8 (aisr: adc input select register) 7 6 5 4 3 2 1 0 ? ? ? ? a d e 3 a d e 2 a d e 1 a d e 0 aisr register defines the port 5 pins as anal og input s or as digit a l i/o, individually . bit 7 ~ 4: not used bit 3 (ade3 ): ad converter enable bit of p53 pin 0 = disable adc3, p53 act s as i/o pin 1 = enable adc3 act s as analog input pin bit 2 (ade2 ): ad converter enable bit of p52 pin 0 = disable adc2, p53 act s as i/o pin 1 = enable adc2 act s as analog input pin
em78p259n/260n 8-bit microprocessor w i th otp rom 46 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) bit 1 (ade1 ): ad converter enable bit of p51 pin 0 = disable adc1, p51 act s as i/o pin 1 = enable adc1 act s as analog input pin bit 0 (ade0 ): ad converter enable bit of p50 pin 0 = disable adc0, p50 act s as i/o pin 1 = enable adc0 act s as analog input pin 6.7.1.2 r9 (adcon: ad control register) 7 6 5 4 3 2 1 0 vrefs c k r 1 c k r 0 adrun a d p d - a d i s 1 a d i s 0 adcon register controls the operation of t he ad conversion and decides which pin should be currently active. bit 7(vrefs): the input source of the adc v r ef 0 = the adc v r ef is connected to vdd (default value), and the p54/vref pin carries out the p54 function 1 = the adc v r ef is connected to p54/vref note t he p54/t cc/ vref pin can not be ap pli e d to t cc and vref at the same ti me. if p54/t cc/vref acts as vref analog input pi n, then cont bit 5 (t s) must be ?0? . t he p54/t cc/vref pin priority is as follow s : p54/tcc/vref pin priority high me dium low vref tcc p54 bit 6 ~ bit 5 (ckr1 ~ ckr0): the adc prescaler oscillator clock rate 00 = 1: 4 (default value) 01 = 1: 16 10 = 1: 64 1 1 = 1: wdt ring oscillator frequency ckr0:ckr1 ope r a t ion mode ma x . ope r a t ion fre que nc y 00 fsco/4 1 mhz 01 fsco/16 4 mhz 10 fsco/64 16mhz 11 internal rc ?
em78p259n/260n 8-bit microprocessor w i th otp rom product specification (v1.0) 06.16.2005 ? 47 (this specification is subject to change without further notice) bit 4 (adrun): adc starts to run. 1 = an ad conversion is started. this bit can be set by software. 0 = reset on completion of the conversion. this bit cannot be reset though software. bit 3 (adpd): adc power-down mode. 1 = adc is operating 0 = switch off the resistor reference to save power even while the cpu is operating. bit 2: not used bit 1 ~ bit 0 (adis1 ~ adis0): analog input select 00 = adin0/p50 01 = adin1/p51 10 = adin2/p52 11 = adin3/p53 these bits can only be changed when the adif bit and the adrun bit are both low. 6.7.1.3 ra (adoc: ad offset calibration register) 7 6 5 4 3 2 1 0 cali sign vof[2] vof[1] vof[0] ? ? ? bit 7 (cali): calibration enable bit for adc offset 0 = calibration disable 1 = calibration enable bit 6 (sign): polarity bit of offset voltage 0 = negative voltage 1 = positive voltage bit 5 ~ bit 3 (vof[2] ~ vof[0]): offset voltage bits. vof[2] vof[1] vof[0] em78p259n/260n ice259n 0 0 0 0lsb 0lsb 0 0 1 2lsb 1lsb 0 1 0 4lsb 2lsb 0 1 1 6lsb 3lsb 1 0 0 8lsb 4lsb 1 0 1 10lsb 5lsb 1 1 0 12lsb 6lsb 1 1 1 14lsb 7lsb bit 2 ~ bit 0: unimplemented , read as ?0?.
em78p259n/260n 8-bit microprocessor w i th otp rom 48 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) 6.7.2 adc data register (addata/rb, addata1h/rc, addata1l/rd) when the ad conversion is completed, the result is loaded to the addata, addata1h and addata1l registers. the adrun bit is cleared, and the adif is set. 6.7.3 adc sampling time the accuracy, linearity, and speed of the succ essive approximation of ad converter are dependent on the properties of the adc and t he comparator. the source impedance and the internal sampling impedance directly affect the time required to charge the sample holding capacitor. the application pr ogram controls the length of the sample time to meet the specified accuracy. gener ally speaking, the program should wait for 2 s for each k ? of the analog source impedance and at least 2 s for the low-impedance source. the maximum recommended impedance for analog source is 10k ? at vdd=5v. after the analog input channel is selected, this acquisition time must be done before the conversion is started. 6.7.4 ad conversion time ckr0 and ckr1 select the conversion time (tct ), in terms of instruction cycles. this allows the mcu to run at a maximum frequenc y without sacrificing the ad conversion accuracy. for the em78p259n/260n, the conversion time per bit is about 4 s. the table below shows the relationship between tct and the maximum operating frequencies. ckr0:ckr1 o peration mod e max. operation frequency max. conversion rate/bit max. conversion rate 00 fsco/4 1 mhz 250khz (4us) 15*4us=60us(16.7khz) 01 fsco/16 4mhz 250khz (4us) 15*4us=60us(16.7khz) 10 fsco/64 16mhz 250khz( 4us) 15*4us=60us(16.7khz) 11 internal rc ? 14kkz (71us) 15*71us=1065us(0.938khz) note pin not used as an analog input pin can be used as a regular i nput or output pin. during conversion, do not perform output in struction to maintain precision for all of the pins. 6.7.5 adc operation during sleep mode in order to obtain a more accurate adc value and reduce power consumption, the ad conversion remains operational during sleep mode. as the slep instruction is executed, all the mcu operations will stop except for the oscillator, tcc, tcca, tccb, tccc and ad conversion. the ad conversion is considered completed as determined by : 1. adrun bit of r9 register is cleared (?0? value). 2. adif bit of re register is set to ?1?.
em78p259n/260n 8-bit microprocessor w i th otp rom product specification (v1.0) 06.16.2005 ? 49 (this specification is subject to change without further notice) 3. adwe bit of the re register is set to ?1.? wake-up from adc conversion (where it remains in operation during sleep mode). 4. wake-up and executes the next instructi on if adie bit of ioce0 is enabled and the ?disi? instruction is executed. 5. wake-up and enters into interrupt vector (address 0x00c) if adie bit of ioce0 is enabled and the ?eni? instru ction is executed. 6. enters into interrupt vector (address 0x 00c) if adie bit of ioce0 is enabled and the ?eni? instructi on is executed. the results are fed into the addata, a ddata1h, and addata1l registers when the conversion is completed. if the adie is enabled, the device will wake up. otherwise, the ad conversion will be shut off, no matter what the status of adpd bit is. 6.7.6 programming process/considerations 6.7.6.1 programming process follow these steps to obtain data from the adc : 1. write to the four bits (ade3 : ade0) on the r8 (aisr) register to define the characteristics of r5 (digital i/o, analog channels, or voltage reference pin) 2. write to the r9/adcon regist er to configure the ad module : a) select the adc input channel (adis1 : adis0) b) define the ad conversion clock rate (ckr1 : ckr0) c) select the vrefs input source of the adc d) set the adpd bit to 1 to begin sampling 3. set the adwe bit, if the wake-up function is employed 4. set the adie bit, if the interrupt function is employed 5. write ?eni? instruction, if the interrupt function is employed 6. set the adrun bit to 1 7. write ?slep? instruction or polling. 8. wait for wake-up, adrun bit is cleared (?0 ? value), interrupt flag (adif) to be set ?1,? or the adc interrupt to occur. 9. read the addata or addata1h and addata1l conversion data registers. if the adc input channel changes at this time, the addata, addata1h, and addata1l values can be cleared to ?0?. 10. clear the interrupt flag bit (adif)
em78p259n/260n 8-bit microprocessor w i th otp rom 50 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) 11. for the next conversion, go to step 1 or step 2 as required. at least 2 tct is required before the next acquisition starts. note in order to obtain accurate values, it is necessary to avoid any data transition on the i/o pins during ad conversion. 6.7.6.2 sample demo programs a. define a general register r_0 == 0 ; indirect addressing register psw == 3 ; status register port5 == 5 port6 == 6 r _ e== 0xe ; interrupt status register b. define a control register ioc50 == 0x5 ; control register of port 5 ioc60 == 0x6 ; control register of port 6 c_int== 0xf ; interrupt control register c. adc control register addata == 0xb ; the contents are the results of adc aisr == 0x08 ; adc input select register adcon == 0x9 ; vrefs ckr1 ckr0 adrun adpd adis2 adis1 adis0 ; 7 6 5 4 3 2 1 0 d. define bits in adcon adrun == 0x4 ; adc is executed as the bit is set adpd == 0x3 ; power mode of adc e. program starts org 0 ; initial address jmp initial ; org 0x0c ; interrupt vector jmp clrre ; ; ; (user program section) ; ; clrre: mov a,re and a, @0bxx0xxxxx ; to clear the adif bit, ?x? by application mov re,a bs adcon, adrun ; to start to execute the next ad conversion if necessary reti initial:
em78p259n/260n 8-bit microprocessor w i th otp rom product specification (v1.0) 06.16.2005 ? 51 (this specification is subject to change without further notice) mov a,@0b00000001 ; to define p50 as an analog input mov aisr,a mov a,@0b00001000 ; to select p50 as an analog input channel, and ad power on mov adcon,a ; to define p50 as an input pin and set clock rate at fosc/16 en_adc: mov a, @0bxxxxxxx1 ; to define p50 as an input pin, and the others iow port5 ; are dependent on applications mov a, @0bxxxx1xxx ; enable the adwe wake-up function of adc, ?x? by application mov re,a mov a, @0bxxxx1xxx ; enable the adie interrupt function of adc, ?x? by application iow c_int eni ; enable the interrupt function bs adcon, adrun ; start to run the adc ; if the interrupt function is employed, the following three lines may be ignored ;if sleep: slep ; ; (user program section) ; or ;if polling: polling: jbc adcon, adrun ; to check the adrun bit continuously; jmp polling ; adrun bit will be reset as the ad conversion is completed ; ; (user program section) ;
em78p259n/260n 8-bit microprocessor w i th otp rom 52 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) 6.8 infrared remote control application/pwm w aveform generation 6.8.1 overview this lsi can easily output infrared carrier or pwm st andard waveform. as illustrated below , the ir and pwm waveform generation function include an 8-bit down count timer/counter , high-time, low-time, and ir cont rol register . the irout pin waveform is determined by ioca0 (ir and tccc scale contro l register), iocb1 (high-time rate, low-tim e rate control regi st er), ioc81 (t cc c co unte r ), ioca1 (high - time regi ste r ), and ioc91 (low-time register). h/ w m o d u lat o r 8 hf irou t ir fca r ri er ft :clk(f osc) lg 8 bi t co unter 8 - to -1 m u x 8b it bin a ry dow n c o un te r a u to-reload buf fer ( t cc c)(i o c 81) 8 b i t co un te r 8- to - 1 m u x 8 b i t c o un te r 8- to - 1 m u x 8 b i t bi na r y d o w n c oun te r 8b it b i n a ry dow n coun te r auto - r e l oa d b u f f e r (high - ti me)(io c a 1 ) a u to-reloa d buf fer (l o w -ti m e) (io c 91) 88 s c al e (i ocb 1 ) s c al e (io c b 1 ) sc a l e (i oc a 0 ) 8 8 un d e rflo w i n terrup t hp wt if lp wt if f i g. 6-10 ir/pw m system block diagram note details of the f c arrier high time w i dth and low time w i dth are explained below : f carrier = ft/ 2 { [1+deci m al tc cc cou n ter val u e (ioc81)] * tccc scale(ioca0) } high time width = { [1+ deci m a l hi gh-ti me v a lu e (ioca1)] * hi gh t i me scal e(ioc b1) } / ft low time width = { [1+ deci m al lo w - time val ue (i oc91)] * low time scal e(iocb1) } / ft where ft is the system clock ft=fosc/1(clk=2) ft=fo sc/2 ( cl k=4 )
em78p259n/260n 8-bit microprocessor w i th otp rom produc t spe c i fic a t ion (v1.0) 06.16.2 005 ? 53 (this specification is subject to change without further notice) when an interrupt is generated by the high time down counter underflow (when enabled), the next instruction will be fetched from address 018 and 01bh (high time and low time respectively). 6.8.2 function description the following figure shows lgp=0 and hf=1 . the irout waveform modulates the fcarrier waveform at low-time segment s of the pulse. fcarrier irout hf ire hi g h time width lo w t i me widt h h i g h time width lo w t i me widt h sta r t f i g. 6-1 1a lgp= 0, hf = 1 , irout pin output w a veform the follo wing figure sho w s lgp=0 and hf= 0 . th e irout wavefo rm can not mo dulate the fcarrier waveform at low-time segment s of the puls e . so irout waveform is determi ned b y the high time wid t h a nd lo w time wid t h i n stea d. this mode can p r o duce st andard pwm waveform fcarrier irout sta r t hf ire hi g h time width lo w t i me widt h h i g h time width lo w t i me widt h f i g. 6-1 1b lgp= 0, hf = 0 , irout pin output w a veform
em78p259n/260n 8-bit microprocessor w i th otp rom 54 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) the following figure shows lgp=0 and hf=1 . the irout waveform modulates the fcarrier waveform at low-time segment s of the pulse. when ire goes low from high, the output waveform of irout will keep tr ansmitting till high-time interrupt occurs. fcarrier irout hf ire ir disable al w ays hi gh- l e vel sta r t hi g h time width lo w t i me widt h h i g h time width lo w t i me widt h f i g. 6-1 1 c lgp= 0, hf = 1 , w hen ire goes low from high, irout pin output s w a veform the followi ng figure sho w s lgp=0 a nd hf= 0 . the irout waveform can not mo dulat e the fcarrier waveform at low-time segment s of the puls e . so irout waveform is determined by high time wid t h and low time wid t h. this mode can produce st andard pwm waveform when ire goes low from high. the output waveform of irout will keep on transmitting till high-time interrupt occurs. fcarrier irout hf ire ir disable al w ays hi gh-l evel sta r t hi g h time width lo w t i me widt h h i g h time width lo w t i me widt h f i g. 6-1 1d lgp= 0, hf = 0 , w hen ire goes low from high, irout pin output w a veform
em78p259n/260n 8-bit microprocessor w i th otp rom produc t spe c i fic a t ion (v1.0) 06.16.2 005 ? 55 (this specification is subject to change without further notice) the following figure shows lgp=1 and hf=1 . when this bit is set to high level, the high-time segment of the pulse is ignored. so, irout waveform output is determined by low-time wid t h. fcarrier irout hf ire ir disable al w ays hi gh-l evel sta r t lo w t i me widt h lo w t i me widt h h i g h time width lo w t i me widt h f i g. 6-1 1e lgp= 1 and hp= 1 , irout pin output w a veform 6.8.3 programming the related registers when defining ir/pwm, refer to the operation of the related registers as shown in the tables below. ir/pwm related control registers a d d r ess name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 x 0 9 i o c 9 0 t ccbhe /0 t ccben/0 t ccbt s /0 t ccbt e /0 0 t cccen/0 t ccct s / 0 t ccct e / 0 0x0a ir cr /ioca0 t cccse /0 t cccs2/0 t cccs1/0 t cccs0/0 i r e / 0 h f / 0 l g p / 0 irout e /0 0x0f imr /iocf0 lpw t ie /0 hpwt ie/0 t cccie/0 t ccbie/0 t cca ie/0 e x i e / 0 i c i e / 0 t c ie/0 0x0b hlt s /iocb1 ht se /0 ht s 2 / 0 ht s1/0 ht s0/0 lt se/0 l t s 2 / 0 l t s 1 / 0 l t s0/0 ir/pwm related status/data registers a d d r ess name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 x 0 f i s r / r f lpwt i f / 0 hpwt if/0 t cccif/ 0 t ccbif/0 t ccaif/0 e x i f / 0 i c i f / 0 t c if/0 0x06 t ccc /ioc81 t c c c 7 / 0 t ccc6/0 t ccc5/0 t ccc4/0 t ccc3/0 t c c c 2 / 0 t c c c 1 / 0 t ccc0/0 0x09 lt r /ioc91 lt r 7 / 0 l t r 6 / 0 l t r5/0 lt r4/0 lt r3/0 lt r 2 / 0 l t r 1 / 0 l t r0/0 0x0a ht r /ioca1 ht r 7 / 0 h t r 6 / 0 h t r5/0 ht r4/0 ht r3/0 ht r 2 / 0 h t r 1 / 0 h t r0/0
em78p259n/260n 8-bit microprocessor w i th otp rom 56 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) 6.9 t i mer/counter 6.9.1 overview timera (tcca) is an 8-bit clo ck cou n te r. ti merb ( t ccb ) is a 16 -bit clo c k c o u n ter. timerc (t ccc) i s an 8-bit clo ck co unter that can b e extended to 1 6 -bit cl ock co unter with program mable scalers. tcca, tccb, and t c cc ca n be rea d and written to, and are cleared at every reset condition. 6.9.2 function description set pr edi c t val ue sy st em cl ock or ext e r n al i n pu t ext e r n al i n p u t tc c c set t c cci f tc c c e n over f l ow tc c a se t t c ca i f tc c a e n ove r f l o w tc c b se t t c cbi f tc c b e n ove r f l o w set pr edi c t val ue s e t p r e d i c t v a l u e ext e r n al i n pu t 8- t o - 1 m u x 8 b i t count e r sy st em c l oc k or sy st em c l ock or tc c c s 1 ~ tc c c s 0 f i g. 6.12 t i mer block diagram each signal and block of the above timer block diagram is described as follows: tccx: t i mer a~c register . tccx increases until it matches with zero, and then reloa d the pre d icted valu e. whe n writ ing a value to tccx, the predi cted value and tccx value become the set value. when reading from tccx, the value will be the tccx direct value. when tccxen is enabled, the reload of the predicted value to tccx, tccxie is also enabled. tccxif will be set at the same time. it is an up counter . under tcca counter (ioc51): ioc51 (tcca) is an 8-bit clo ck counte r . it can be rea d , written, an d clea red on any reset condition and is an up counter. note t cca timeout period [1/f osc x (256-t cca cnt) x 1(clk= 2)] t cca timeout period [1/f osc x (256-t cca cnt) x 2(clk= 4)] under tccb counter (ioc61): an 8-bit c l oc k c o unter is for the leas t s i gnific ant byte of tccbx (tccb). it c a n be read, written, and cleared on any reset condition and is an up counter.
em78p259n/260n 8-bit microprocessor w i th otp rom product specification (v1.0) 06.16.2005 ? 57 (this specification is subject to change without further notice) under tccbh / msb counter (ioc71): an 8-bit clock counter is for the most significant byte of tccbx (tccbh). it can be read, written, and cleared on any reset condition. when tccbhe (ioc90) is ?0,? then tccb h is disabled. when tccbhe is?1,? then tccb is a 16-bit length counter. note when tccbh is disabled: tccb timeout period [1/fosc x ( 256 - tccb cnt ) x 1(clk=2)] tccb timeout period [1/fosc x ( 256 - tccb cnt ) x 2(clk=4)] when tccbh is enabled: tccb timeout period {1/fosc x [ 65536 - (tccbh * 256 + tccb cnt)] x 1(clk=2)} tccb timeout period {1/fosc x [ 65536 - (tccbh * 256 + tccb cnt)] x 2(clk=4)} under tccc counter (ioc81): ioc81 (tccc) is an 8-bit clock counter. it can be read, written, and cleared on any reset condition. if hf (bit 2 of ioca0) = 1 and ire (bit 3 of ioca0) = 1, tccc counter scale uses the low-time segments of t he pulse generated by fcarrier frequency modulation (see fig. 6-11 in section 6.8.2, function description ). then the tccc value will be the tccc predicted value. when hp = 0 or ire = 0, the tccc is an up counter. note under tccc up counter mode: tccc timeout period [1/fosc x scaler (ioca0) x (256-tccc cnt) x 1(clk=2)] tccc timeout period [1/fosc x scaler (ioca0) x (256-tccc cnt) x 2(clk=4)] when hp = 1 and ire = 1, the tccc counter scale uses the low-time segments of the pulse generated by fcarrier frequency modulation. note under ir mode: fcarrier = ft/ 2 { [1+decimal tccc count er value (ioc81)] * tccc scale (ioca0) } ft is system clock: ft = fosc/1 (clk=2) ft = fosc/2 (clk=4)
em78p259n/260n 8-bit microprocessor w i th otp rom 58 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) 6.9.3 programming the related registers when defining tccx, refer to the operation of it s related registers as shown in the t ables below . tccx related control registers : a d d r ess name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 x 0 8 i o c 8 0 0 0 cpout / 0 c os1/0 c os0/0 t ccaen /0 t ccat s /0 t ccat e /0 0 x 0 9 i o c 9 0 t ccbhe /0 t ccben /0 t ccbt s /0 t ccbt e /0 0 t cccen /0 t ccct s /0 t ccct e /0 0x0a ir cr /ioca0 t cccse /0 t cccs2 /0 t cccs1/ 0 t cccs0 /0 i r e / 0 h f / 0 l g p / 0 irout e /0 0x0f imr /iocf0 lpwt e / 0 hpwt e/0 t cccie/0 t ccbie/0 t ccaie/0 e x i e / 0 i c i e / 0 t c ie/0 related tccx s t atus/dat a registers : a d d r ess name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 x 0 f i s r / r f lpwt f / 0 hpwt f/0 t cccif/0 t ccbif/0 t ccaif/0 e x i f / 0 i c i f / 0 t c if/0 0x05 t cca /ioc51 t c c a 7 / 0 t c c a 6 / 0 t cca5/0 t cca4/0 t cca3/0 t c c a 2 / 0 t c c a 1 / 0 t cca0/0 0x06 t ccb /ioc61 t c c b 7 / 0 t c c b 6 / 0 t ccb5/0 t ccb4/0 t ccb3/0 t c c b 2 / 0 t c c b 1 / 0 t ccb0/0 0x07 t ccbh /ioc71 t ccbh7 /0 t ccbh6 /0 t ccbh5 /0 t ccbh4 /0 t ccbh3 /0 t ccbh2 /0 t ccbh1 /0 t ccbh0 /0 0x08 t ccc /ioc81 t c c c 7 / 0 t ccc6/0 t ccc5/0 t ccc4/0 t ccc3/0 t c c c 2 / 0 t c c c 1 / 0 t ccc0/0 6.10 comp arator em78p259n/260n has one comp arator which has t w o a nalo g input s an d one output. the comp arator can be employed to wake-up from the sleep mode. figure below shows the circuit of the comp arator . ci n - - + cmp ci n+ co ci n+ ci n - o u tput 30 m v f i g. 6.13 comp arat or operating mode
em78p259n/260n 8-bit microprocessor w i th otp rom produc t spe c i fic a t ion (v1.0) 06.16.2 005 ? 59 (this specification is subject to change without further notice) 6.10.1 external reference signal the an alog si gnal that is p r ese n ted at ci n? co mp are s to the sign al at cin+. th e digit a l output (co ) o f the com p a r a t or is a d ju ste d ac co rdin gly by t a kin g the f o llowin g note s into considerations: note t he reference signal must be betw een vss and vdd. t he reference voltage can be applied to either pin of the comparator. t h reshold detector applications may be of the same reference. t he comparator can operate from the sa me or different reference sources. 6.10.2 comparator outputs the comp ared result is stored in the cmpout of ioc80. the comp arator output s are sent to co (p64) through programming bit 4 & bit 3 of the ioc80 regi st er to <1,0 >. see t able und er se ction 6.2 . 4, ioc80 (com p a rator and tcca control registers) for comp arator/op select bit s function description . the following figure shows the comp arator output block diagram. q q en en d d to c0 to cpif to cmpout cmrd cmrd from other comparator reset from op i/o f i g. 6-14 t he output conf iguration of a comp arator
em78p259n/260n 8-bit microprocessor w i th otp rom 60 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) 6.10.3 using a comparator as an operation amplifier the comp arator can be used as an operati on amplifier if a feedback resistor is externally connected from the input to the out put. in this case, t he schmitt trigger can be disabled for power saving purposes, by se tting bit 4, bit 3< cos1, cos0> of the ioc80 re giste r to <1,1>. se e t able und er section 6.2.4, ioc80 (com p a rator and t c ca control registers) for comp arator/op select bit s function description . note under operation amplifier: t he cmpie (ioce0.4), cmpw e (re.2) , and cmpif (re.4) bits are invalid. t he comparator interrupt is invalid. t he comparator w a ke-up is invalid. 6.10.4 comparator interrupt cmpie (ioce0.4) must be enabled for the ?eni? instruction to t a ke ef fect interrupt is triggered whenever a change occurs on the comp arator output pin the actual change on the pin can be determined by reading the bit cmpout , ioc80<5>. cmpif (re.4), the comp arator interrupt flag, can only be cleared by sof t ware 6.10.5 wake-up from sleep m ode if the cmpwe bit of the re registe r is set to ?1,? the comp a r ato r re mains a c tive and the interrupt remains functional, even under sleep mode. if a mismatch occurs, the change will wake up the device from sleep mode. the po we r co nsum ption sh ould be t a ken into con s id eration for the b enefit of ene rgy conservation. if the function is unemployed during sleep mode, turn of f the comp arator before entering into sleep mode. the comp arator is considered completed as determined by : 1. cos1 and cos0 bit s of ioc80 register setting select s comp arator . 2. cmpif bit of re regis t er is s e t to ?1?. 3. cmpwe bit of re regis t er is s e t to ?1 ?. w a kes-up from comp arator (where it remains in operation during sleep mode) 4. w a kes-up and executes the next instructi on, if cmpie bit of ioce0 is enabled and the ?disi? instruction is executed. 5. w a ke-up and enters into interrupt vector ( address 0x00f), if adie bit of ioce0 is enabled and the ?eni? inst ruction is executed 6. enters into interrupt vector (address 0x 00f), if cmpie bit of ioce0 is enabled and the ?eni? instruct ion is executed.
em78p259n/260n 8-bit microprocessor w i th otp rom product specification (v1.0) 06.16.2005 ? 61 (this specification is subject to change without further notice) 6.11 oscillator 6.11.1 oscillator modes the em78p259n/260n can be operated in four different oscillator modes, such as high xtal oscillator mode (hxt), low xtal osc illator mode (lxt), external rc oscillator mode (erc), and rc oscillator mode with internal rc oscillator mode (irc). you can select one of them by programming the osc2, ocs1, and osc0 in the code option register. the oscillator modes defined by osc2, ocs1, and osc0 are described below. oscillator modes osc2 osc1 osc0 erc 1 (external rc oscillator mode); p70/osco acts as p70 0 0 0 erc 1 (external rc oscillator mode); p70/osco acts as osco 0 0 1 irc 2 (internal rc oscillator mode); p70/osco acts as p70 0 1 0 irc 2 (internal rc oscillator mode); p70/osco acts as osco 0 1 1 lxt 3 (low xtal oscillator mode) 1 1 0 hxt 3 high xtal oscillator mode) (default) 1 1 1 1 under erc mode, osci is us ed as oscillator pin. os co/p70 is defined by code option word0 bit6 ~ bit4. 2 under irc mode, p55 is normal i/o pi n. osco/p70 is defined by code option word0 bit6 ~ bit4. 3 under lxt and hxt modes; osci and osco ar e used as oscillator pins. these pins cannot and should not be defined as normal i/o pins. note the transient point of the system fr equency between hxt and lxy is around 400khz. the maximum operating frequency limit of crysta l/resonator at different vdds, are as follows : conditions vdd max. freq. (mhz) 2.3 4 3.0 8 two clocks 5.0 20
em78p259n/260n 8-bit microprocessor w i th otp rom 62 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) 6.11.2 crystal oscillator/ceramic resonators (xtal) the em78p2 59n/2 60 n ca n be driven by an exter nal clo ck sig nal throu gh the osci pin as illustrated below . os ci os co e m 78p25 9n e m 78p26 0n f i g. 6-15 external clock input circuit in most applications, pin osci and pin os co can be connected with a cryst a l or ceramic resonator to generate oscillation. fig. 6-16 below depict s such circuit. the same applies to the hxt mode and the lxt mode. osci em 78p259n em 78p260n os c o xt a l rs c2 c1 f i g. 6-16 cryst al/resonator circuit the following t able provides the recommended values for c1 and c2. since each resonator has it s own attribute, you should re fer to the resonator specifications for the approp riate value s of c1 a nd c2. rs, a seri al re si stor , may be requ ired for a t st rip cu t cryst a l or low frequency mode. cap a citor selection guide for cryst a l oscillator or ceramic resonators : oscillator ty pe fre que nc y mode fre que nc y c1 (pf) c2 (pf) 4 5 5 k h z 1 0 0 ~ 1 5 0 100~ 1 5 0 2.0 mhz 20~ 40 20~ 40 ceramic resonators hxt 4.0 mhz 10~ 30 10~ 30 32.768khz 25 15 100khz 25 25 lxt 200khz 25 25 4 5 5 k h z 2 0 ~ 4 0 20~ 1 5 0 1.0 mhz 15~ 30 15~ 30 2.0 mhz 15 15 cry s tal oscillator hxt 4.0 mhz 15 15
em78p259n/260n 8-bit microprocessor w i th otp rom produc t spe c i fic a t ion (v1.0) 06.16.2 005 ? 63 (this specification is subject to change without further notice) circuit diagrams for serial and p a rallel modes cryst a l/resonator : os ci em 7 8 p259 n em 7 8 p260 n c 740 4 330 330 xta l 74 04 74 04 f i g. 6-17 serial mode cryst al/resonator circuit diagram em 7 8 p2 5 9 n em 7 8 p2 6 0 n os ci 74 04 74 04 c1 c2 10 k 4. 7 k vd d 10 k 10 k 95 "- f i g. 6-18 parallel mode cryst al/resonator circuit diagram 6.11.3 external rc oscillator m ode for some applications that do not require precise timing calculation, the rc oscillator (fig. 6-19 right) could of fer you wit h ef f e ct iv e co st sav i n g s. nev e rt h e le ss , it should be noted that the frequency of the rc oscillator is influenced by the supply volt age, the values of the resistor (rext), the cap a citor (cext), and even by the ope ration temperature. moreove r , th e frequency also changes slightly from one chip to another due to the manufacturing process variation. osc i em78p 25 9n em78p 26 0n vc c re xt c ext f i g. 6-19 exter nal r c oscill ator mode circu it in order to ma int a in a st a b le system frequ ency , the valu es of the cext should b e no less than 20pf , and that of rext sho u ld be no greate r than 1m ? . if the fr eque ncy can not be kept within this range, the frequency can be af fected easily by noise, humidity , and leakage. the smaller the rext in the rc oscillator is , the faster it s frequency will be. on the contrary , for very low rext values, for inst ance, 1 k ? , the oscillator will become unst able because the nmos cannot dischar ge the cap a cit ance current correctly .
em78p259n/260n 8-bit microprocessor w i th otp rom 64 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) based on the above reasons, it must be kept in mind that all supply voltage, the operation temperature, the components of the rc oscillator, the package types, and the way the pcb is layout, have cert ain effect on the system frequency. the rc oscillator frequencies: cext rext average fosc 5v,25 c average fosc 3v,25 c 3.3k 3.5 mhz 3.2 mhz 5.1k 2.5 mhz 2.3 mhz 10k 1.30 mhz 1.25 mhz 20 pf 100k 140 khz 140khz 3.3k 1.27 mhz 1.21 mhz 5.1k 850khz 820khz 10k 450khz 450khz 100 pf 100k 48khz 50khz 3.3k 560khz 540khz 5.1k 370khz 360khz 10k 196khz 192khz 300 pf 100k 20khz 20khz note : 1. measured on dip packages 2. design reference only 3. the frequency drift is about ? 30% 6.11.4 internal rc oscillator mode em78p259n/260n offers a versatile inter nal rc mode with default frequency value of 4mhz. internal rc oscillator mode has ot her frequencies (1mhz, 8mhz, and 455khz) that can be set by code option (word1 ), rcm1, and rcm0. the table below describes the em78p259n/260n internal rc drift with voltage, temperature, and process variation. internal rc drift rate (ta=25
, vdd=5v? 5%, vss=0v) drift rate internal rc frequency temperature (-40
~+80
) voltage (2.3v~5.5v) process total 4mhz 10% 5% 4% 19% 8mhz 10% 6% 4% 20% 1mhz 10% 5% 4% 19% 455mhz 10% 5% 4% 19% theoretical values, for reference only. actual va lues may vary depending on the actual process.
em78p259n/260n 8-bit microprocessor w i th otp rom produc t spe c i fic a t ion (v1.0) 06.16.2 005 ? 65 (this specification is subject to change without further notice) 6.12 power-on considerations any microcon troller is not warranted to st ar t operating prop erly bef ore the power supply st abilizes in steady st ate. the em78p 259n/260n por volt age range is 1.9 ~ 2.1v . under customer application, when power is switched off , vdd must drop below 1.9v and remains at off st ate for 10 s before power can be switched on again. subsequently , the em78p259n/260n will reset and work normally . the extra external reset circuit will work well if vdd rises fast enough (50ms or less). however , under critical applications, extra devices are st ill required to assist in solving power-on problems. 6.12.1 programmable wdt time-out period the option word (wdtps) is used to define the wdt time-out period (18ms 5 or 4.5ms 6 ). theoretically , the range is from 4.5ms or 18ms. for most cryst a l or ceramic resonato r s, the lowe r the operat io n freq uen cy is, the longe r is the required set-u p time. 6.12.2 external power-on reset circuit the ci rcuit sh own in the foll owin g figure i m pleme n t s a n external rc to produ ce a reset pulse. the pulse wid t h (time const ant) should be kept long enough to allow vdd to rea c h the min i mum operating volt age. this circuit is u s ed when the power su pply has a s l ow power ris e time. bec ause the c u rr ent leak age from the /reset pin is about 5 a, it is recomme nded that r should n o t be greate r than 40 k. this way , the volt age at pin /reset is held below 0.2v . the diode (d) act s as a short circuit at power-down. the ?c? cap a citor is discharged rapidly and fully . rin, the current-limit ed resistor , prevent s high c u rrent dis c harge or esd (elec t ros t atic dis c harge) from flowing into pin /reset . em 78p259n em 78p260n / r eset vd d d r rin c f i g. 6-20 external pow e r - on reset circuit vdd= 5v , w d t time-out period = 16.5ms 30%. vdd= 3v , w d t time-out period = 18ms 30%. 5v , w d t time-out period = 4.2ms 30%. vdd= 3v , w d t time-out period = 4.5ms 30%. 5 6 vdd=
em78p259n/260n 8-bit microprocessor w i th otp rom 66 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) 6.12.3 residual voltage protection when the battery is replaced, device power (vdd) is removed but the residual volt age remains. the residual volt age may trip below vdd minimum, but not to zero. this condition may cause a poor power-on reset. fig. 6-21 and fig. 6-22 show how to create a protection circuit against residual volt age. em 78 p25 9 n em 78 p26 0 n / r eset vd d 100 k q1 1 n 46 84 10 k 33 k vd d f i g. 6-21 residual v o lt age protection circuit 1 / r ese t vd d q1 vdd r3 r2 r1 em 7 8 p2 59n em 7 8 p2 60n f i g. 6-22 residual v o lt age protection circuit 2
em78p259n/260n 8-bit microprocessor w i th otp rom product specification (v1.0) 06.16.2005 ? 67 (this specification is subject to change without further notice) 6.13 code option em78p259n/260n has two code option words and one customer id word that are not part of the normal program memory. word 0 word1 word 2 bit12 ~ bit0 bit12 ~ bit0 bit12 ~ bit0 6.13.1 code option register (word 0) word 0 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ? ? ? type clks enwdtb osc2 osc1 osc0 hlp pr2 pr1 pr0 bit 12 ~ 10: not used (reserved). these bits are set to ?1? all the time bit 9 (type): type selection for em78p259n or em78p260n 0 = em78p260n 1 = em78p259n (default) bit 8 (clks): instruction period option bit 0 = two oscillator periods 1 = four oscillator periods (default) refer to section 6.15 for instruction set bit 7 (enwdtb): watchdog timer enable bit 0 = enable 1 = disable (default) bit 6, 5 & 4 (osc2, osc1 & osc0): oscillator modes selection bits oscillator modes osc2 osc1 osc0 erc 1 (external rc oscillator mode); p70/osco acts as p70 0 0 0 erc 1 (external rc oscillator mode); p70/osco acts as osco 0 0 1 irc 2 (internal rc oscillator mode); p70/osco acts as p70 0 1 0 irc 2 (internal rc oscillator mode); p70/osco acts as osco 0 1 1 lxt 3 (low xtal oscillator mode) 1 1 0 hxt 3 high xtal oscillator mode) (default) 1 1 1 1 under erc mode, osci is us ed as oscillator pin. os co/p70 is defined by code option word0 bit6 ~ bit4. 2 under irc mode, p55 is normal i/o pi n. osco/p70 is defined by code option word0 bit6 ~ bit4. 3 under lxt and hxt modes; osci and osco ar e used as oscillator pins. these pins cannot and should not be defined as normal i/o pins. note the transient point of the system fr equency between hxt and lxy is around 400khz.
em78p259n/260n 8-bit microprocessor w i th otp rom 68 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) bit 3 (hlp): power consumption selection 0 = low power consumption, applies to working frequency at or below 4mhz 1 = high power consumption, applies to working frequency above 4mhz bit 2 ~ 0 (pr2 ~ pr0): protect bits pr2 ~ pr0 are protect bits. each protect status is as follows : pr2 pr1 pr0 protect 0 0 0 enable 0 0 1 enable 0 1 0 enable 0 1 1 enable 1 0 0 enable 1 0 1 enable 1 1 0 enable 1 1 1 disable 6.13.2 code option register (word 1) word 1 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - - rcout nrhl nre wdtps cyes c3 c2 c1 c0 rcm1 rcm0 bits 12 ~ 11: not used (reserved). these bits are set to ?1? all the time bit 10 (rcout): system clock output enable bit in irc or erc mode 0 = osco pin is open drain 1 = osco output system clock bit 9 (nrhl): noise rejection high/low pulses define bit. int pin is falling edge trigger 0 = pulses equal to 8/fc [s] is regarded as signal 1 = pulses equal to 32/fc [s] is regarded as signal (default) note the noise rejection function is tu rned off under the lxt and sleep mode. bit 8 (nre): noise rejection enable 0 = disable noise rejection 1 = enable noise rejection (default), but under low xtal oscillator (lxt) mode, the noise rejection circuit is always disabled.
em78p259n/260n 8-bit microprocessor w i th otp rom product specification (v1.0) 06.16.2005 ? 69 (this specification is subject to change without further notice) bit 7 (wdtps) : wdt time-out period selection bit wdt time watch-dog time * 1 18 ms 0 4.5 ms * theoretical values, for reference only bit 6 (cyes): instruction cycle selection bit 0 = one instruction cycle. 1 = two instructions cycle (default) bit 5, 4, 3, & bit 2 (c3, c2, c1, c0 ) : calibrator of internal rc mode c3, c2, c1, & c0 must be set to ?1? only (auto-calibration). bit 1 & bit 0 (rcm1, rcm0): rc mode selection bits rcm 1 rcm 0 frequency (mhz) 1 1 4 1 0 8 0 1 1 0 0 455khz 6.13.3 customer id register (word 2) word 2 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x x x x x x x x x x x x x bit 12 ~ 0 : customer?s id code 6.14 instruction set each instruction in the instruction set is a 13-bit word divided into an op code and one or more operands. normally, all instructi ons are executed within one single instruction cycle (one instruction consists of 2 oscilla tor periods), unless the program counter is changed by instructions "mov r2,a," "add r2,a," or by instructions of arithmetic or logic operation on r2 (e.g., "sub r2,a," "bs(c) r2,6," "clr r2," etc.). in this case, these instructions need one or two instruct ion cycles as determined by code option register cyes bit. in addition, the instruction set has the following features : 1. every bit of any register c an be set, cleared, or tested directly. 2. the i/o registers can be regarded as general registers. that is, the same instruction can operate on i/o registers.
em78p259n/260n 8-bit microprocessor w i th otp rom 70 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) the symbol "r" represents a register designat or that specifies which of the registers (including operational registers and general-pur pose registers) is to be utilized by the instruction. the symbol "b" represents a bi t field designator that selects the value for the bit located in the register "r" that is affected by the operation. the symbol "k" represents an 8 or 10-bit constant or literal value. the following are the em78p259n/260n instruction set instruction binary hex mnemonic operation status affected 0 0000 0000 0000 0000 nop no operation none 0 0000 0000 0001 0001 daa decimal adjust a c 0 0000 0000 0010 0002 contw a cont none 0 0000 0000 0011 0003 slep 0 wdt, stop oscillator t,p 0 0000 0000 0100 0004 wdtc 0 wdt t,p 0 0000 0000 rrrr 000r iow r a iocr none 1 0 0000 0001 0000 0010 eni enable interrupt none 0 0000 0001 0001 0011 disi disable interrupt none 0 0000 0001 0010 0012 ret [top of stack] pc none 0 0000 0001 0011 0013 reti [top of stack] pc, enable interrupt none 0 0000 0001 0100 0014 contr cont a none 0 0000 0001 rrrr 001r ior r iocr a none 1 0 0000 01rr rrrr 00rr mov r,a a r none 0 0000 1000 0000 0080 clra 0 a z 0 0000 11rr rrrr 00rr clr r 0 r z 0 0001 00rr rrrr 01rr sub a,r r-a a z,c,dc 0 0001 01rr rrrr 01rr sub r,a r-a r z,c,dc 0 0001 10rr rrrr 01rr deca r r-1 a z 0 0001 11rr rrrr 01rr dec r r-1 r z 0 0010 00rr rrrr 02rr or a,r a vr a z 0 0010 01rr rrrr 02rr or r,a a vr r z 0 0010 10rr rrrr 02rr and a,r a & r a z 0 0010 11rr rrrr 02rr and r,a a & r r z 0 0011 00rr rrrr 03rr xor a,r a r a z 0 0011 01rr rrrr 03rr xor r,a a r r z 0 0011 10rr rrrr 03rr add a,r a + r a z,c,dc 0 0011 11rr rrrr 03rr add r,a a + r r z,c,dc 0 0100 00rr rrrr 04rr mov a,r r a z 0 0100 01rr rrrr 04rr mov r,r r r z 0 0100 10rr rrrr 04rr coma r /r a z 0 0100 11rr rrrr 04rr com r /r r z 0 0101 00rr rrrr 05rr inca r r+1 a z 0 0101 01rr rrrr 05rr inc r r+1 r z 0 0101 10rr rrrr 05rr djza r r-1 a, skip if zero none 0 0101 11rr rrrr 05rr djz r r-1 r, skip if zero none 0 0110 00rr rrrr 06rr rrca r r(n) a(n-1),r(0) c, c a(7) c 0 0110 01rr rrrr 06rr rrc r r(n) r(n-1),r(0) c, c r(7) c 0 0110 10rr rrrr 06rr rlca r r(n) a(n+1),r(7) c, c a(0) c 0 0110 11rr rrrr 06rr rlc r r(n) r(n+1),r(7) c, c r(0) c 0 0111 00rr rrrr 07rr swapa r r(0-3) a(4-7),r(4-7) a(0-3) none 0 0111 01rr rrrr 07rr swap r r(0-3) ? r(4-7) none 0 0111 10rr rrrr 07rr jza r r+1 a, skip if zero none
em78p259n/260n 8-bit microprocessor w i th otp rom product specification (v1.0) 06.16.2005 ? 71 (this specification is subject to change without further notice) instruction binary hex mnemonic operation status affected 0 0111 11rr rrrr 07rr jz r r+1 r, skip if zero none 0 100b bbrr rrrr 0xxx bc r,b 0 r(b) none 2 0 101b bbrr rrrr 0xxx bs r,b 1 r(b) none 3 0 110b bbrr rrrr 0xxx jbc r,b if r(b)=0, skip none 0 111b bbrr rrrr 0xxx jbs r,b if r(b)=1, skip none 1 00kk kkkk kkkk 1kkk call k pc+1 [sp],(page, k) pc none 1 01kk kkkk kkkk 1kkk jmp k (page, k) pc none 1 1000 kkkk kkkk 18kk mov a,k k a none 1 1001 kkkk kkkk 19kk or a,k a k a z 1 1010 kkkk kkkk 1akk and a,k a & k a z 1 1011 kkkk kkkk 1bkk xor a,k a k a z 1 1100 kkkk kkkk 1ckk retl k k a,[top of stack] pc none 1 1101 kkkk kkkk 1dkk sub a,k k-a a z,c,dc 1 1111 kkkk kkkk 1fkk add a,k k+a a z,c,dc 1 this instruction is applicable to ioc50 ~ iocf0, ioc51 ~ iocc1 only. 2 this instruction is not recommended for rf operation. 3 this instruction cannot operate under rf. 7 absolute maximum ratings items rating temperature under bias -40 c to 85 c storage temperature -65 c to 150 c input voltage vss-0. 3v to vdd+0.5v output voltage vss-0.3v to vdd+0.5v working voltage 2.5v to 5.5v working frequency dc to 20mhz
em78p259n/260n 8-bit microprocessor w i th otp rom 72 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) 8 dc electrical characteristics (ta=25 c, vdd=5.0v 5%, vss=0v) symbol parameter condition min typ max unit xtal: vdd to 5v dc 20 mhz xtal: vdd to 3v two cycle with two clocks dc 8 mhz erc: vdd to 5v r: 5.1k ? , c: 100 pf f 30% 830 f 30% khz fxt irc: vdd to 5 v 8mhz,4mhz, 1mhz, 455khz f 30% f f 30% hz irc1 irc:vdd to 5v rcm0:rcm1=1:1 3.84 4.0 4.16 mhz irc2 irc:vdd to 5v rcm0:rcm1=1:0 7.68 8.0 8.32 mhz irc3 irc:vdd to 5v rcm0:rcm1=0:1 0.96 1.0 1.06 mhz irc4 irc:vdd to 5v rcm0:rcm1=0:0 436.8 455 473.2 khz vihrc input high threshold voltage (schmitt trigger ) osci in rc mode 3.5 v vilrc input low threshold voltage (schmitt trigger ) osci in rc mode 1.5 v iil input leakage current for input pins vin = vdd, vss -1 0 1 a vih1 input high voltage (schmitt trigger ) ports 5, 6, 7 3.75 v vil1 input low voltage (schmitt trigger ) ports 5, 6, 7 1.25 v viht1 input high threshold voltage (schmitt trigger ) /reset 2.0 v vilt1 input low threshold voltage (schmitt trigger ) /reset 1.0 v viht2 input high threshold voltage (schmitt trigger ) tcc,int 3.75 v vilt2 input low threshold voltage (schmitt trigger ) tcc,int 1.25 v vihx1 clock input high voltage osci in crystal mode 3.5 v vilx1 clock input low voltage osci in crystal mode 1.5 v ioh1 output high voltage (ports 5, p60~66,p70) voh = vdd-0.5v -3.7 ma ioh2 output high voltage (ir out (port67)) voh = vdd-0.5v -10 ma iol1 output low voltage (ports 5, p60~66,p70) vol = gnd+0.5v 10 ma iol2 output low voltage (ir out (port67)) vol = gnd+0.5v 15 ma iph pull-high current pull-high acti ve, input pin at vss -70 -75 -80 a ipl pull-low current pull-low active, input pin at vdd 35 40 45 a isb1 power down current all input and i/o pins at vdd, output pin floating, wdt disabled 1.0 2.0 a isb2 power down current all input and i/o pins at vdd, output pin floating, wdt enabled 6.0 10 a icc1 operating supply current at two clocks (vdd to 3v) /reset= 'high', fosc=32khz (crystal type,clks="0"), output pin floating, wdt disabled 15 20 a
em78p259n/260n 8-bit microprocessor w i th otp rom product specification (v1.0) 06.16.2005 ? 73 (this specification is subject to change without further notice) icc2 operating supply current at two clocks (vdd to 3v) /reset= 'high', fosc=32khz (crystal type,clks="0"), output pin floating, wdt enabled 15 25 a icc3 operating supply current at two clocks /reset= 'high', fosc=4mhz (crystal type, clks="0"), output pin floating, wdt enabled 1.9 2.2 ma icc4 operating supply current at two clocks /reset= 'high', fosc=10mhz (crystal type, clks="0"), output pin floating, wdt enabled 3.0 3.5 ma note: 1. these parameters ar e hypothetical (not test ed) and are provided for design reference use only. 2. data under minimum, typical, & maximum (mi n, typ, & max) column s are based on hypothetical results at 25
. these data are for design reference only. 8.1 ad converter characteristics (vdd=2.5v to 5.5v, vss=0v, ta=25
) symbol parameter condition min. typ. max. unit v aref 2.5 ? vdd v v ass analog reference voltage v aref - v ass 2.5v vss ? vss v vai analog input voltage ? v ass ? v aref v ivdd 750 850 1000 ua iai1 ivref analog supply current vdd=v aref =5.0v, v ass =0.0v (v referenced from vdd) ?10 0 +10 ua ivdd 500 600 820 ua iai2 ivref analog supply current vdd=v aref =5.0v, v ass =0.0v (v referenced from vref) 200 250 300 ua iop op current vdd=5.0v, op used output voltage swing 0.2v to 4.8v 450 550 650 ua rn resolution vdd=v aref =5.0v, v ass =0.0v 10 11 ? bits ln linearity error vdd = 2.5 to 5.5v ta=25
0 4 8 lsb dnl differential nonlinear error vdd = 2.5 to 5.5v ta=25
0 0.5 0.9 lsb fse full scale error vdd=v aref =5.0v, v ass =0.0v 0 4 8 lsb oe offset error vdd=v aref =5.0v, v ass =0.0v 0 2 4 lsb zai recommended impedance of analog voltage source ? 0 8 10 k tad adc clock period vdd=v aref =5.0v, v ass =0.0v 4 ? ? us tcn ad conversion time vdd=v aref =5.0v, v ass =0.0v 15 ? 15 tad adiv adc op input voltage range vdd=v aref =5.0v, v ass =0.0v 0 ? v aref v 0 0.2 0.3 adov adc op output voltage swing vdd=v aref =5.0v, v ass =0.0v, rl=10k 4.7 4.8 5 v adsr adc op slew rate vdd=v aref =5.0v, v ass =0.0v 0.1 0.3 ? v/us psr power supply rejection vdd=5.0v0.5v 0 ? 2 lsb note: 1. these parameters ar e hypothetical (not test ed) and are provided for design reference use only. 2. there is no current c onsumption when adc is off ot her than minor leakage current. 3. ad conversion result will not decrease when an increase of input voltage and no missing code will result.
em78p259n/260n 8-bit microprocessor w i th otp rom 74 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) 8.2 comp arator (op) characteristics (vdd = 5.0v , vss=0v , t a =25
) sy mbol parameter condition min. ty p. max. unit s r s l e w r a t e 0 . 1 0 . 2 v/us ivr i n p u t v o l t a g e r a n g e vdd = 5 .0v, v ss = 0 . 0 v 0 5 v 0 0 . 2 0 . 3 ovs output voltage sw i n g vd = 5 .0v, v ss =0.0v, rl=10k ? 4 . 7 4 . 8 5 v iop supply current of op 250 350 500 ua ico supply current of comparator 300 ua psr r pow e r-supply rejection r a t i o n f o r o p vdd= 5.0v, v ss = 0 . 0 v 50 60 70 db v s o p e r a t i n g r a n g e 2 . 5 5 . 5 v note: t hese parameters are hy pothetical (not tested) and are pr ovided for design reference only . 8.3 device characteristics the graphs below were derived based on a limited number of samples and they are provided for reference only . hence, the device characteristic shown herein cannot be guaranteed as fully accurate. in these gr aphs, the dat a maybe out of the specified operating warranted range. i rc o s c fr e que nc y ( v d d = 3 v ) 0 1 2 3 4 5 6 7 8 9 -4 0 - 2 0 0 25 50 70 85 tem p erature (
) frequency (m hz) f i g. 8-1 internal rc osc f r equency vs. t e mperature, vdd= 3v
em78p259n/260n 8-bit microprocessor w i th otp rom produc t spe c i fic a t ion (v1.0) 06.16.2 005 ? 75 (this specification is subject to change without further notice) i r c o s c f r e q u e n c y ( vdd=5 v ) 0 1 2 3 4 5 6 7 8 9 10 -4 0 - 2 0 0 25 50 70 85 t e m p er at u r e (
) 'sfrvfodz . ) [
f i g. 8-2 internal rc osc f r equency vs. t e mperature, vdd= 5v 9 ac electrical characteristic (t a=25 c, vdd=5v 5%, vss= 0v) sy mbol parameter conditions min ty p max unit dclk input clk duty cy cle 4 5 5 0 5 5 % cry s tal ty pe 100 dc ns ti n s instruction cy cle time (clks="0") rc ty pe 500 dc ns t t cc t cc input period ( t ins+ 20)/n* n s t d rh device reset hold time ta = 2 5 c 1 1 . 3 1 6 . 2 2 1 . 6 m s t r st /reset pulse w i dth ta = 2 5 c 2 0 0 0 n s t w dt w a tchdog timer period ta = 2 5 c 1 1 . 3 1 6 . 2 2 1 . 6 m s t s et input pin setup time 0 n s t hold input pin hold time 1 5 2 0 2 5 n s t delay output pin delay time cload= 20pf 4 5 5 0 5 5 n s t d rc erc delay time ta = 2 5 c 1 3 5 n s note: 1. n = selected prescaler ratio 2. t w dt1 : t he option w o rd1 (w dt ps) is used to define the oscillator set-up time. w d t timeout length is the same as set-up time (18ms). 3. t w dt2 : t he option w o rd1 (w dt ps) is used to define the oscillator set-up time. w d t timeout l ength is the same as set-up time (4.5ms). 4. t hese parameters are hy pothet ical (not tested) and are prov ided for design reference only . 5. data under minimum, ty pical, & maximum (mi n, t y p, & max) columns are based on hy pothetical results at 25
. t hese data are for design reference use only . 6. t he w a tchdog timer duration is det ermined by code option w o rd1 (w dt ps).
em78p259n/260n 8-bit microprocessor w i th otp rom 76 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) 10 timing diagrams r e set t i mi ng (c lk =" 0") clk / r eset nop inst ruct ion 1 e xec uted td r h tc c input ti ming (c lk s=" 0 ") clk tc c ttc c ti n s a c t e s t ing : input is dr iv e n a t v dd-0 . 5 v for logic "1 " , a nd gnd+ 0 . 5 v for logic " 0 ".t i m i ng measu remen t s are made at 0.75vdd f o r lo g i c "1",and 0.25vdd f o r lo g i c "0". a c test i n p u t/ ou tput w a v e form vdd-0 . 5v g n d + 0.5v 0.75v d d 0.25v d d t est p o i n t s 0.75v d d 0.25v d d
em78p259n/260n 8-bit microprocessor w i th otp rom produc t spe c i fic a t ion (v1.0) 06.16.2 005 ? 77 (this specification is subject to change without further notice) appendix a. package types summary otp mcu packag e t y p e pin count packag e size e m 7 8 p 2 5 9 n p d i p 1 8 3 0 0 m i l e m 7 8 p 2 5 9 n m s o p 1 8 3 0 0 m i l e m 7 8 p 2 6 0 n p d i p 2 0 3 0 0 m i l e m 7 8 p 2 6 0 n m s o p 2 0 3 0 0 m i l e m 7 8 p 2 6 0 n k m s s o p 2 0 2 0 9 m i l b packaging configurations b.1 18-lead plastic dual in line (pdip) { 300 mil
em78p259n/260n 8-bit microprocessor w i th otp rom 78 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) b.2 18-lead plastic small outline (sop) { 3 0 0 m i l
em78p259n/260n 8-bit microprocessor w i th otp rom produc t spe c i fic a t ion (v1.0) 06.16.2 005 ? 79 (this specification is subject to change without further notice) b.3 20-lead plastic shrink small outline (ssop) { 209 mil
em78p259n/260n 8-bit microprocessor w i th otp rom 80 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) b.4 20-lead plastic dual-in-line (pdip) { 300 mil
em78p259n/260n 8-bit microprocessor w i th otp rom produc t spe c i fic a t ion (v1.0) 06.16.2 005 ? 81 (this specification is subject to change without further notice) b.5 20-lead plastic small outline (sopp) { 300 mil
em78p259n/260n 8-bit microprocessor w i th otp rom 82 ? product specification (v1.0) 06.16.2005 (this specification is subject to change without further notice) c quality assurance and reliability test category test conditions remarks solderability solder temperature=245 5
, for 5 seconds up to the stopper using a rosin-type flux step 1: tct, 65
(15mins)~150
(15mins), 10 cycles step 2: bake at 125
, td (durance)=24 hrs step 3: soak at 30 c/60% d td (durance)=192 hrs pre-condition step 4: ir flow 3 cycles (pkg thickness 2.5mm or pkg volume 350mm3 ----225 5
) (pkg thickness 2.5mm or pkg volume 350mm3 ----240 5
) for smd ic (such as sop, qfp, soj, etc) temperature cycle test -65
(15mins)~150
(15mins), 200 cycles pressure cooker test ta =121
, rh=100%, pressure=2 atm, td (durance)= 96 hrs high temperature / high humidity test ta=85
, rh=85% d td (durance)=168 , 500 hrs high-temperature storage life ta=150
, td (durance)=500, 1000 hrs high-temperature operating life ta=125
, vcc=max. operating voltage, td (durance) =168, 500, 1000 hrs latch-up ta=25
, vcc=max. operating voltage, 150ma/20v esd (hbm) ta=25
, t? 3kv t esd (mm) ta=25
, t? 300v t ip_nd,op_nd,io_nd ip_ns,op_ns,io_ns ip_pd,op_pd,io_pd, ip_ps,op_ps,io_ps, vdd-vss(+),vdd_vss (-)mode c.1 address trap detect an address trap detect is one of the mcu embedded fail-safe functions that detects mcu malfunction caused by noise or the like. whenever the mcu attempts to fetch an instruction from a certain section of rom, an in ternal recovery circuit is auto started. if a noise caused address error is detected, t he mcu will repeat execution of the program until the noise is eliminated. the mcu will then continue to execute the next program.

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